• boundary concept

    Hi all,

    I am new to protocols AHB and AXI.

    can anyone explain why there is 4kb boundary in AXI and why there is 1 kb boundary in AHB?

    Also what these boundaries are for? Does they represent the maximum slave size?

  • Transfer size in AMBA AXI

    Hi, I am not so clear about the concept of transfer size in AMBA AXI. My question is how to calculate wrap_boundary in wrap based data transfer when Number_Bytes (The maximum number of bytes in each data transfer) is changing in each transfer within a…

  • AXI-4 questions

    Hello,

    I am pretty new to AMBA protocol and I am specifically interested in AXI-4. I have a few fundamental questions related to AXI-4 and I would appreciate if anyone can answer these.

    1) I would like to know how read and write address requests issued…

  • AMBA AXI CACHE

    i am not able to understand working of this CACHE signal pleas explain with simple example.

    thank you!

  • How to map tag RAM banks to data cache lines in Cortex-R5?

    Hi,

    We are using Cortex-R5F. Through the AXI slave interface, we are accessing the data cache data RAM, tag RAM and dirty RAM. We would like to know how we can associate the bits found in the data RAM with the bits found in the tag RAM. For example,…

  • Problems about signal dependencies in AXI spec

    Hi,

    In AXI4/5 spec (IHI0022F), it listed a set of signal dependencies for read and write transactions.

    My problem is in Figure A3-7 AXI4 and AXI5 write transaction handshake dependencies. It noted that "Dependencies on the assertion of WVALID also require…

  • AXI read response in error case

    Hi,

    In the AXI spec it is mentioned that , even in case of ERROR response, the slave needs to respond with the exact number of beats and indicate the response with each beat.

    Now my question here is if the response is going to be ERROR(lets say SLVERR…

  • Why AXI4 changed the definition of AxCACHE?

    Hi,

    In AXI4, spec changed the definition of the definition of AxCACHE[3:2] from Write Allocate/Read Allocate to be Allocate/Other Allocate.

    But is there any concrete reason for this change? Actually I found some related statements from spec, but I couldn…

  • Store operations where the cache line is already cached (ACE protocol)

    In Section C1.3 Channel Overview of the AMBA_AXI_and_ACE protocol specifications, It is mentioned under "Store operations where the cache line is already cached" as :

    The initiating master component requests a unique copy of the cache line…

  • Removal of WID's in AMBA AXI4

    Hi ,

       What is the purpose of removing ID's (WID) in AXI4 ?

    If it because of reduction of pin count then We lost the " Write Data Interleaving" and "Out Of Order " Transaction features. Can you please tell me if any other reasons...(Arm Spec says.…

  • AXI4 - read data interleaving

    Hi Folks,

    We need a clarification on Read Data Interleaving on AXI4

    Read Data Interleaving is supported in AXI4 and following is my understanding on Data Interleaving:

    Multiple Read commands can be executed simultaneously and data interleaving is supported…

  • AXI Protocol -  Strobe Signal Value

    how to calculate the value of strobe signal in axi?

  • AXI protocol - Unaligned data transfer definition

    IN axi,what is unaligned data transfer??