Hello,

i didnt find at spec any note about the waited write transfer.

for example 

T1 : NONSEQ + write transfer  + HREADY is high

T2: HREADY dropped + HTRANS is idle - HWDATA ?

does the HWDATA have to be the right data or it can be any junk ? and only when…

1. How barrier instructions like `dmb ishld` and `ldar/stlr` translate to ACE barrier transactions?

I am curious about how barrier instructions which will only affect specific types of memory operations would translate to ACE barrier transactions.

I supposed…

Hello to all,

I have a question about AMBA3 AHB-Lite and AHB5 Specification:

In AMBA3 AHB-Lite Specification, "Table 6-2 Active byte lanes for a 32-bit big-endian data bus" is mean word-invariant big-endian or byte-invariant big-endian? Why its…

Can somebody please explain how barrier transactions in ACE work?

Thanks in advance.