D-Cache read problem in EL2 mode ARM V8

Hello, 

I am working on  EL2 mode ARM V8 ,

Problem I am facing when I enable D-cache then I am not able to read the data. 

My boot flow is EL3 to EL2 and in EL2 snippet of code is below 

1 stp x29, x30 [sp,#32]

2 mrs     x0, sctlr_el2

3 orr     x0, x0, #CTRL_C_BIT

4  msr     sctlr_el2, x0

5 ldp x29, x30 [sp,#32]

Here  I checked all x30, sp etc are valid and point to valid memory and this DDR location is accessible from other core. 

After line 4, at line 5 I am getting random values in x29, x30 

In case i comment lune 4, then boot works fine, 

I am wondering , why this enable cache is leading to bad behavior

FYI, 

If I stay in EL3 mode only then changing above code like 

1 stp x29, x30 [sp,#32]

2 mrs     x0, sctlr_el3

3 orr     x0, x0, #CTRL_C_BIT

4  msr     sctlr_el3, x0

5 ldp x29, x30 [sp,#32]

 

works fine as well. 

Thanks for help, why enabling d-cache in EL2 mode is leading to random/corrupted values 

thx

Parents Reply Children
No data
More questions in this forum
There are no posts to show. This could be because there are no posts in this forum or due to a filter.