I am working on EL2 mode ARM V8 ,
Problem I am facing when I enable D-cache then I am not able to read the data.
My boot flow is EL3 to EL2 and in EL2 snippet of code is below
1 stp x29, x30 [sp,#32]
2 mrs x0, sctlr_el2
3 orr x0, x0, #CTRL_C_BIT
4 msr sctlr_el2, x0
5 ldp x29, x30 [sp,#32]
Here I checked all x30, sp etc are valid and point to valid memory and this DDR location is accessible from other core.
After line 4, at line 5 I am getting random values in x29, x30
In case i comment lune 4, then boot works fine,
I am wondering , why this enable cache is leading to bad behavior
If I stay in EL3 mode only then changing above code like
2 mrs x0, sctlr_el3
4 msr sctlr_el3, x0
works fine as well.
Thanks for help, why enabling d-cache in EL2 mode is leading to random/corrupted values
From the PG:" The caches in the processor must be invalidated before caching of data and instructions is enabled in any of the Exception levels."Also, I'd add an ISB after enabling the cache.
Above what is mentioned in PG, is already in place
I missed that part in snippet of code, but i am doing invalidation and isb
OK, kinda weird code ;-)
Anyway, you cannot be sure your store reached RAM before enabling the cache.
I'd say you need a "DSB" after the store.
But this is also does not help,
Can you refer me some code, in C or assembly, Which I can use to read cache contents (L1/L2/L3)
To update here, I got things working,
For this I need to flush L3 cache in EL3 before switching to EL2
Could you tell me how to flush L3 cache in EL3?
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