why the inter-core SGI interrupt cannot be trigged on GICv3 hardware

My hareware environment:

1.  a ARMv8 processor , which  runs in 64bit EL3 and 32bit EL2&EL1.

2. a GICv3 interrupt controller

Running in 32bit hyp mode,  I try to send a SGI interrupt from core0 to core1, but core1 cannot receive this interrupt. Below are what I've tried.

1. I use ICC_SGI1R to send the interrupt. GICD_SGIR cannot be used because "affinity routing" is enabled.

2. Group0, Group1NS and Group1S interrupt are enabled in GICD_CTLR

3. Write GICR_ISENABLER0 to enable SGI interrupt

4. The IRQ/FIQ are unmasked in core1's cpsr
5. Group1 intersuprt is enabled in core1's ICC_IGRPEN1 register

But after writting to  ICC_SGI1R, I can not find valid bit in pending state register, and core1's ICC_IAR register are also always invalid.

Do you have any suggestions with this issue?

Thanks in advance.

Parents
  • A couple of thoughts...

    • You said that you'd written GICR_ISENABLER0 to enable the SGI you're sending.  Which core's Redistributor did you write to?  It needs to have been that of receiving core (or both of course).
    • Did you also write GICR_IGROUPR0 to set the interrupt as NS.G1?  (Note, you'll need to do this in Secure state)
    • Have you written GICR_WAKER to make the cores as awake? (You'll need to do this for sender and receiver)
      • You need do the writes of GICR_WAKER before configuring the CPU IF.  Writing a CPU IF reg (other than SRE regs) when the core is marked as asleep is UNPREDICTABLE.
    • What's the priority of the SGI (GICR_IPRORITYRn, of the receiver) and what's the PMR value?
    • Does GICR_ISPENDR0 (of the receiver's Redistributor) show the interrupt as pending after the write to ICC_SGI1R?
      • Strictly, you'll need a DSB between the write of the ICC_SGI1R and the read of the GICR_ISPENDR0
Reply
  • A couple of thoughts...

    • You said that you'd written GICR_ISENABLER0 to enable the SGI you're sending.  Which core's Redistributor did you write to?  It needs to have been that of receiving core (or both of course).
    • Did you also write GICR_IGROUPR0 to set the interrupt as NS.G1?  (Note, you'll need to do this in Secure state)
    • Have you written GICR_WAKER to make the cores as awake? (You'll need to do this for sender and receiver)
      • You need do the writes of GICR_WAKER before configuring the CPU IF.  Writing a CPU IF reg (other than SRE regs) when the core is marked as asleep is UNPREDICTABLE.
    • What's the priority of the SGI (GICR_IPRORITYRn, of the receiver) and what's the PMR value?
    • Does GICR_ISPENDR0 (of the receiver's Redistributor) show the interrupt as pending after the write to ICC_SGI1R?
      • Strictly, you'll need a DSB between the write of the ICC_SGI1R and the read of the GICR_ISPENDR0
Children