I don't understand the meaning of busy state behavior from ARM IHI0033B spec.
I draw the waveform to ask busy state behavior. The following is my questions.
Q1. For Read response. If the master enters busy state, which time phase does
master get correct data from the slave. data_a1_x or data_a1_y or data_a1_z or data_a1_q ?
PS: data_a1_x ≠ data_a1_y ≠ data_a1_z ≠ data_a1_q
Please see fig1
Q2: For write tansaction, if the master enters busy state which time phase doesslave can get correct data from master. data_a1_x or data_a1_y or data_a1_z or data_a1_q ?PS: data_a1_x ≠ data_a1_y ≠ data_a1_z ≠ data_a1_
Please see fig2.
Sorry, I forgot to mark the pictures. The first picture is fig 1 and the second picture is fig 2.
"data_a1_x" in both questions.
The current address phase HTRANS value does not affect the completion of a previous transfer data phase, only HREADY does. So in both cases the completion of the SEQ transfer before the BUSY transfers start only needs to wait for HREADY=1, and that is at the end of "data_a1_x" in both your examples.
Note that once you are in the data phases of your BUSY transfers, there is no defined data value, so HWDATA and HRDATA are undefined for those data phases ("data_a1_y", "data_a1_z" and "data_a1_q")..
So, according your answer, for read transfer, the master must receive the read data in T2-T3.
For write transfer, the slave must receive the write data in T2-T3. Because data_a1_y, data_a1_z and data_a1_q are undefined for those data phases in both case.
Is my understanding correct?
If the slave was NOT able to supply the requested HRDATA or sample the HWDATA value, it would signal wait states on HREADY.
As HREADY is high in the T2-T3 cycle highlighted, the SEQ transfer data phase HAS completed, the "addr1" data transfers completed.
BUSY transfers do not require the slave to perform any data transfer, so they are essentially "ignored" by the slave, and the slave simply drives HREADY high and HRESP=OKAY.
I mean, in BUSY state, it indicates that master can't provide valid address phase in this cycle, but dose master have capability to receive RDATA in BUSY state?
If master has capability to receive RDATA in BUSY state, Does ARM® AMBA® 5 AHB Protocol Specification describe this behavior?
Have you understood that AHB transfer occur in two phases, the address phase when the master tells the system what it wants to do, and the data phase when the requested data transfer is performed ?
The address phase of one transfer coincides with the data phase of the previous transfer.
Only the slave can delay the completion of a transfer data phase, using the HREADY signal.
So if a master is signaling a BUSY transfer address phase because it is not yet able to move on to the next SEQ transfer in a burst, that has no effect on the previous transfer data phase completing. The master MUST be able to receive read data for that previously issued transfer.
If the master is a multi-cycle design, in other words, master need 2T to handle data phase, could master not receive data in the SEQ state?
If I use AHB bus as the IC's interface, there may be timing issue for master or slave, they don't have enough time to prepare or receive data, what does AHB do because your constrain is so strict.
From my opinion, busy state is the master idle state when the master cannot prepare address phase or data phase. From the Spec " When a master uses the BUSY transfer type the address and control signals must reflect the next transfer in the burst. "in page 3-30, I thought when there is something wrong with command/ data control signals, the master can enter busy state to tell the salve its idle state and then the master can have time to prepare next transfer.
Because I didn't see any strong words to show that master MUST receive/send data in T2-T3, I thought master have flexible timing to receive/send data. I thought this is a Good point at AHB bus protocol. But if not, AHB bus protocol has strict timing constrain for master and slave. What could I do if I meet timing issue?
Only the final diagram is the correct one to show the relationship between the AHB address and data phases of a transfer. The protocol is pipelined, with the data phase following immediately after the address phase.
If a master is not able to commit to the next address phase transfer in a burst it can issue a BUSY transfer (or an IDLE if there is no burst ongoing), and if a slave performing a NONSEQ or SEQ transfer data phase cannot complete that transfer in one cycle it can hold HREADY low for a number of cycles to add wait states.
Once a NONSEQ or SEQ transfer has entered the data phase, the master must be able to accept the read data returned by the slave, or it must be able to drive the correct write data. The master cannot stall a data phase transfer completion.
Sorry for these disjointed statements, but I'm not now too sure what you are asking.