What is the correct data in BUSY state?

I don't understand the meaning of busy state behavior from ARM IHI0033B spec.

I draw the waveform to ask busy state behavior. The following is my questions.

 

Q1. For Read response. If the master enters busy state, which time phase does

master get correct data from the slave.  data_a1_x or data_a1_y or data_a1_z or data_a1_q ?

PS: data_a1_x ≠ data_a1_y ≠ data_a1_z ≠ data_a1_q

Please see fig1

 

Q2: For write tansaction, if the master enters busy state which time phase does
slave can get correct data from master. data_a1_x or data_a1_y or data_a1_z or data_a1_q ?
PS: data_a1_x ≠ data_a1_y ≠ data_a1_z ≠ data_a1_

Please see fig2.

Parents
  • "data_a1_x" in both questions.

    The current address phase HTRANS value does not affect the completion of a previous transfer data phase, only HREADY does. So in both cases the completion of the SEQ transfer before the BUSY transfers start only needs to wait for HREADY=1, and that is at the end of "data_a1_x" in both your examples.

    Note that once you are in the data phases of your BUSY transfers, there is no defined data value, so HWDATA and HRDATA are undefined for those data phases ("data_a1_y", "data_a1_z" and "data_a1_q")..

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  • "data_a1_x" in both questions.

    The current address phase HTRANS value does not affect the completion of a previous transfer data phase, only HREADY does. So in both cases the completion of the SEQ transfer before the BUSY transfers start only needs to wait for HREADY=1, and that is at the end of "data_a1_x" in both your examples.

    Note that once you are in the data phases of your BUSY transfers, there is no defined data value, so HWDATA and HRDATA are undefined for those data phases ("data_a1_y", "data_a1_z" and "data_a1_q")..

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