I don't understand the meaning of busy state behavior from ARM IHI0033B spec.
I draw the waveform to ask busy state behavior. The following is my questions.
Q1. For Read response. If the master enters busy state, which time phase does
master get correct data from the slave. data_a1_x or data_a1_y or data_a1_z or data_a1_q ?
PS: data_a1_x ≠ data_a1_y ≠ data_a1_z ≠ data_a1_q
Please see fig1
Q2: For write tansaction, if the master enters busy state which time phase doesslave can get correct data from master. data_a1_x or data_a1_y or data_a1_z or data_a1_q ?PS: data_a1_x ≠ data_a1_y ≠ data_a1_z ≠ data_a1_
Please see fig2.
Sorry, I forgot to mark the pictures. The first picture is fig 1 and the second picture is fig 2.