GICv3 ITS -- CPU accesses to GITS_TRANSLATER

The GICv3's ITS register GITS_TRANSLATER is meant to be used as a doorbell for MSI-capable peripherals.

What is the architected behavior when a PE, rather than such a peripheral, accesses the register? The GICv3 spec does not make that point entirely clear, although I expect writes to have no effect, as the PE has no way to provide the out-of-band DeviceID.

This is an important point for hypervisors giving passthrough access to MSI-capable peripherals to (untrusted) virtual machines. Using 2-stage address translation to isolate the virtual machines and their peripherals, such a hypervisor could set up the MMU and SMMU with the same Stage 2 translation tables (this scenario is explicitly encouraged by Arm). To allow MSI writes to go through the SMMU, the Stage 2 translation tables would have to include a writable mapping to GITS_TRANSLATER. But then, the MMU would also let the PE write to GITS_TRANSLATER.

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