How to enable FIQ in lpc2129?

I am a complete beginner to embedded systems.

I started with lpc2129 and have done few programs on different things.

Although user manual gives description about vectored and non vectored interrupts,

There is no info on FIQ.

Arm documentation says __irq address should be placed at 0x0000001C.

F_BIT address 0x40

But startup code says to reset the F_BIT to enable FIQ mode.

Also some changes should be done in trustzone.

If someone can explain this?

I am really sorry for asking a basic thing but im from cs background and new to embedded.

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  • The FIQ can be closed off to you by the chip manufacturer using trust zone extensions.

    The Trust zone creates a Secure world and a normal world. The secure world has its own supervisor, user and memory space. The idea is for secure operations to be routed so they never leave the chip and cannot be traced even if you scan the pins on the bus. I think in OMAP it is used for some cryptography operations.

    On Reset the core starts in secure mode. It sets up the secure monitor (gateway between secure and non-secure world) and at this time FIQ can be setup to be routed to the monitor. I think it is the SCR.FIQ bit that may be set and then all FIQs ignore the value of CPSR.F and go to monitor mode. Check out the ARM ARM but if I remember correctly if this is happening there is no way for you to know from nonsecure OS code. Then the monitor will reset the Normal world registers and doing an exception return with PC set to the reset exception vector.

    The core will take an interrupt to monitor mode, do its thing and return.

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  • The FIQ can be closed off to you by the chip manufacturer using trust zone extensions.

    The Trust zone creates a Secure world and a normal world. The secure world has its own supervisor, user and memory space. The idea is for secure operations to be routed so they never leave the chip and cannot be traced even if you scan the pins on the bus. I think in OMAP it is used for some cryptography operations.

    On Reset the core starts in secure mode. It sets up the secure monitor (gateway between secure and non-secure world) and at this time FIQ can be setup to be routed to the monitor. I think it is the SCR.FIQ bit that may be set and then all FIQs ignore the value of CPSR.F and go to monitor mode. Check out the ARM ARM but if I remember correctly if this is happening there is no way for you to know from nonsecure OS code. Then the monitor will reset the Normal world registers and doing an exception return with PC set to the reset exception vector.

    The core will take an interrupt to monitor mode, do its thing and return.

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