Debugging a Cortex-M0 Hard Fault

There's many references to Debugging a Hard Fault on Cortex-M3 & M4; eg

niallcooling's Developing a Generic Hard Fault handler for Armv7-M

also:

http://supp.iar.com/Support/?Note=23721

https://community.freescale.com/thread/306244 - which references  http://www.keil.com/appnotes/files/apnt209.pdf

http://www.freertos.org/Debugging-Hard-Faults-On-Cortex-M-Microcontrollers.html

http://support.code-red-tech.com/CodeRedWiki/DebugHardFault

But hard to find anything specifically for Cortex-M0 (or M0+)

The Armv6-M Architecture Reference Manual seems to be saying that many of the features that the above references rely upon are not provided in Cortex-M0; eg, there's no CFSR and no HFSR.

I have managed to implement a Hard Fault handler (from suggestions above), and it is called when a Hard Fault occurs - just not sure how much of the information is actually valid/useful once I'm there...

Cheers,

Andy.

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  • Hi Andy,

    While a fault status registers (and certain fault types) are not present in Armv6m, the basic process should remain the same. From the Hard Fault handler:

    1. Test bit 2 of the LR to determine whether the MSP or PSP was being used
    2. Read the Stack Frame pointed to by the Stack Pointer discovered in Step 1
    3. The Program Counter in the Stack Frame (xSP+0x18) will tell you the address of the instruction that caused the fault.

    jyiu's The Definitive Guide to the Arm Cortex-M0 has a good chapter detailing Fault Handling on the Cortex-M0.

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  • Hi Andy,

    While a fault status registers (and certain fault types) are not present in Armv6m, the basic process should remain the same. From the Hard Fault handler:

    1. Test bit 2 of the LR to determine whether the MSP or PSP was being used
    2. Read the Stack Frame pointed to by the Stack Pointer discovered in Step 1
    3. The Program Counter in the Stack Frame (xSP+0x18) will tell you the address of the instruction that caused the fault.

    jyiu's The Definitive Guide to the Arm Cortex-M0 has a good chapter detailing Fault Handling on the Cortex-M0.

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