There's many references to Debugging a Hard Fault on Cortex-M3 & M4; eg
niallcooling's Developing a Generic Hard Fault handler for Armv7-M
https://community.freescale.com/thread/306244 - which references http://www.keil.com/appnotes/files/apnt209.pdf
But hard to find anything specifically for Cortex-M0 (or M0+)
The Armv6-M Architecture Reference Manual seems to be saying that many of the features that the above references rely upon are not provided in Cortex-M0; eg, there's no CFSR and no HFSR.
I have managed to implement a Hard Fault handler (from suggestions above), and it is called when a Hard Fault occurs - just not sure how much of the information is actually valid/useful once I'm there...
Glad you posted it here. Thanks Joseph, really helped me a lot. Was looking for this, I couldn't see this anywhere, finally an answer. There are really stuff that is hard to start with Cortex-M0.
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