Hi to all,
I am developing an Operating System for ArmV8-A that ensures spatial isolation among the tasks using memory virtualization. I already wrote the MMU driver successfully and now I am trying to develop bare-metal driver for the SMMU-500 embedded inside the SoC Xilinx Zynq Ultrascale+.
My code starts the execution in EL2 after Arm Trusted Firmware. In that exception level it does only some configurations and then it goes in EL1. Here it tries to configure the SMMU to work with Gigabit Ethernet Controller that has a DMA inside.
When an ethernet frame arrives, the Controller raises an interrupt but I cannot see any changes in the expected memory addresses. Futhermore the SMMU doesn't raise any interrupt to notify a fault.
I configure the SMMU in this way:
1) In SMMU_sCR0 the bit-fileds CLIENTPD, USFCFG, GFRE, GFIE, GCFGFIE, GCFGFRE are set.2) All SMMU_SMRn registers are written to 0;3) All SMMU_CBn_SCTLR are written to 0;4) 0 is written in the CBIndex field of SMMU_S2CR0;5) The StreamID of the Etherner Controller is written in the register SMMU_SMR0. Furthermore the bit valid of this register is asserted;6) SMMU_CB0_TCR, SMMU_CB, SMMU_CB0_MAIR are configured in the same way of the MMU.7) SMMU_CB0_SCTLR is configured as following (SCTLR_CFIE | SCTLR_CFRE | SCTLR_AFE | SCTLR_TRE | SCTLR_M | SCTLR_S1_ASIDPNE);8) The CLIENTPD field is clean in the register SMMU_sCR0.
There is some way to debug the SMMU? Can I see the bus transactions to check if the Enthernet Controller requires a write to the correct physical address? Can I know if the SMMU does the translation?
With respect to DMA, did you invalidate the cache for the memory the DMA writes to?
The whole memory is marked as shareable in the translation table, so I think that the cache invalidation isn't necessary. Am I wrong?
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