Hi,
I tested SGI interrupt latency, it seems that GIC3.0's SGI interrupt latency are much bigger than GIC2.0.
How to test:
GIC3.0:
1. read timestamp(t01)
2. core0 write ICC_SGI0R_EL1 to trigger core1, read timestamp(t02)
3. isr in core1, read timestamp(t03)
GIC2.0:
1. read timestamp(t11)
2. core0 write GICD_SGIR to trigger core1, read timestamp(t12)
3. isr in core1, read timestamp(t13)
Result is (had think about the time of reading timestamp):
1. (t02 - t01) nearly 3 times bigger than (t12 - t11) which means system register cost more time than access to memory mapped memory.
2. (t03 - t02) nearly 2 times bigger than (t13 - t12) which means interrupt latency of GIC3.0 are much bigger than GIC 2.0
Is this normal? Any help will be appreciated! Thanks!
BR,
Peng
Which cores? The same on both SoCs? The same bus clock? You should provide some basic information. And/or ask yourself what influences your meassurements.
Hi Bastian,
Sorry for my negligence!
Both are ARM Cortex-A53 SMP 4 cores.
The clock with GIC3.0 are lower about 10% than the one with GIC2.0.
But this can not lead to 2-3 times decline. Do you agree?
Thanks!
Factor 2 to 3 sounds like there is some other "bug".Did you check if your timestamp() measurement is correct by takeing the time of a loop on both SoCs?
Just to be sure you are not comparing apples with pears.Another question: You are running the 100% identical software (appart from low-level setup).
Timestamp is quite stable, we used it for more other tests.
Yes, the routine are same, only different parts are two GIC driver.
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