The Chinese Semiconductor Market: Rapidly Accelerating

At just under 14 minutes, with a top speed of 300km/hour, my commute to an airport on public rail transportation has never been faster! I wasn't on the high-speed public rail systems that typically come to mind, such as the TGV in Europe or the Shinkansens in Japan. In this case, it was actually the sleek, fast and efficient Shanghai Maglev. As I sped from Pudong to Shanghai International Airport, it struck me that the Maglev is a good metaphor for the rapid transformation of the Chinese semiconductor market.

Just like China's trains, the country's semiconductor industry has undergone a dramatic and rapid transformation. Just a few years ago, a vast majority of fabless end customers and design service providers in China were focusing on chip design at mainstream 130 and 180nm technologies. Now 65nm is much more common, and in the next several years, 40nm will become the predominant production process for China.

ARM's dual approach of education and training for SoC engineers coupled with strong customer support in the AsiaPac region is starting to bear fruit with all of the top 11 China fabless companies now licensing ARM processors and seven out of eleven licensing the ARM Artisan® 40nm physical IP. This includes high-volume mobile customers like Spreadtrum, which are now successfully shipping parts using ARM's complete platform of 9-track and 12-track multi-channel logic libraries, embedded memory compilers, general purpose IO (GPIO) and POP^TM IP solutions for Cortex^TM-A5 processors.

Using advanced techniques like range-based optimization and dynamic banking, the new memory compilers can achieve up to 33% smaller area and 30% lower power at equivalent performance compared to competitive solutions.

Compared to other vendors whose standard cells are either not footprint-compatible or are sparsely populated for long channel, ARM's multi-channel logic libraries are both: true footprint compatible and comprehensive (all functions available for C40 and C50). This offers a simple multi-channel flow in addition to the existing multi-Vt flow and can potentially reduce leakage up to 75% without compromising performance or area (based on Cortex-A9 benchmarks).

I would argue that some of the greatest potential for die size reduction (>20%) for pad limited designs could be achieved from ARM's multi-row GPIO architecture. While significantly better at reducing overall SoC pitch than the generic staggered IO, the ARM GPIO library retains the programmable drive strengths/slew rates flexibility to support multiple applications with a single GDSII.

Successfully getting a competitive, silicon-proven 40LP physical IP platform to the market in time for rapid AsiaPac adoption has been a challenging and rewarding enterprise. We expect the momentum of ARM's 40LP physical IP adoption to continue accelerating over the coming years - just like the sleek, fast and efficient Shanghai Maglev.