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Quality of Service in ARM Systems: An Overview

Ashley Stevens
September 26, 2014

Introduction

Whether it’s the latest consumer multimedia device with ultra-high resolution display, or highperformance, long up-time enterprise hardware, almost all performance-oriented SoC systems are dependent on high bandwidth and low latency external memory systems to deliver within cost and performance boundaries. With the cost and power of adding additional or higher performance memory controllers being prohibitive in many or indeed most cases, schemes that can get the best performance from existing or more modest memory systems are desirable.
 
Quality-of-Service (QoS) in the SoC interconnect and memory controller simultaneously enables low latency for highly latency-sensitive masters like CPUs, hard real-time demands from real-time devices and sufficient but not excessive bandwidth for potentially greedy masters like GPUs and high-performance DMAs.
 
Various QoS mechanisms are supported within ARM System on Chip (SoC) IP. This paper presents an overview of the mechanisms available for the SoC designer to chose from and discusses the scenarios where they may be most advantageous.
 
QoS+QVN-FINAL.pdf
Anonymous
  • Offline over 3 years ago

    Very useful document! ! !

    I have one question for QoS with AXI4:

    Can one master have multiple QoS values?

    Meaning one master issues requests with different QoS values but all with same AXI ID and the interconnect network arbitrates between these requests based on QoS value and may give response out of order. I see an issue that if the AXI IDs are same for request and the responses are out of order then it may violate the in order requirement within an ID.

    Possible solution will be

    a. One master is issuing unique QoS value

    b. If one master is issuing multiple QoS values then the AXI IDs will be different for  those request.

    Thanks in anticipation.

    Best Regards,

    Tarun

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