Performance Analysis and Verification of SoC Interconnects

In the world of the System on Chip (SoC) end users have come to expect a richer web experience, full HD video, full HD gaming and sophisticated applications leading to embedded processors becoming more powerful; wired and wireless communications becoming faster; and graphics and audio becoming more capable.  As a result, the role of the interconnect that connects all these data producers and consumers together is becoming more demanding. To meet the increased demands, new protocols (AXI4^TM,ACE^TM,ACE-Lite^TM), new Corelink™NIC-400™ Interconnect, with new features such as Quality of Service(QoS-400^TM), QoS Virtual Networks (QVN-400™), and Memory Management Units are being added to the interconnect. All of these have to be thoroughly understood to get the best performance out of your SoC.

A typical SoC (Figure 1) is constructed around a cascade of interconnects, with each interconnect being a configuration of an interconnect design IP (CoreLink^TM Network Interconnect NIC-301^TM, NIC-400^TM, and CoreLink^TMCCI-400^TM Cache Coherent Interconnect) and each interconnect design IP having a huge number of configuration and programming options.

Figure 1: Typical SoC with cascadedinterconnect

When building such an SoC, it is important to ensure that the SoC Interconnect is functionally correct and that it supports the latency and bandwidth requirements of the intended application use cases.  This can be very challenging, as it requires the creation of a testbench for the specific use of verifying the interconnect and measuring performance, or waiting until the full SoC is implemented and running on an emulation platform (which is very late in the design cycle).

The need for cycle accurate, early design cycle performance analysis and verification of SoC Interconnects led to the development of the Cadence Interconnect Workbench.
 
Cadence Interconnect Workbench
So, how does the Interconnect Workbench (Figure 2) help you do early design cycle performance analysis and verification of SoC interconnects?  The answer is automation!

Figure 2:Interconnect Workbenchoperations

Starting with the IP-XACT description of the interconnect RTL, Interconnect Workbench generates a UVM e or UVM SystemVerilog testbench that configures all the Verification IP required to provide stimulus and responses to the interconnect.  There are 2 flavors of the testbench — one tailored to the goal of verification, and one tailored to the goal of performance analysis(which adds Performance Generators and a Performance Monitor to the testbench). As you can imagine, this capability alone can remove weeks from a project schedule.

Once the testbench is generated the next step is to simulate, either interactively for debug or in a regression for analysis later.  Again, Interconnect Workbench helps here by generating the infrastructure required to run the simulations on Cadence^®Incisive^® Enterprise Simulator, and can also use Cadence^®Incisive^® Enterprise Manager for regression management.

The final step in the process is analysis. Performance analysis is done using the Interconnect Workbench Performance Analyzer (Figure 3) which adds the ability to graphically analyze, review and interpret the performance metrics gathered during a performance regression.  Verification analysis(Figure 4) is done via Cadence Incisive vManager; the Verification Plan (vPlan)that Interconnect Workbench generates gives a good starting point for MetricDriven Verification (MDV).

Figure 3: Performance Analysis with Interconnect Workbench Performance Analyzer

Figure4: Verification Analysis with Enterprise Manager

To see the Interconnect Workbench in action, please take a look at the videobelow that was recorded at DAC2012 in San Francisco. 

More Information
If you're interested in additional information please contact: Stewart Penmanv (spenman@cadence.com), Nick Heaton (nickh@cadence.com), Steve Brown (stevebr@cadence.com). 
ARM Partner Blogger:
Stewart Penman, Principal Solutions Engineer, Cadence Design Systems. Stewart Penman graduated from The University of Edinburgh with a Master of Engineering Honors Degree in Electronics, initially working as a Display Systems Engineer for Pilkington Optronics in Glasgow.  Since joining Cadence in 1999,Stewart has completed many services engagements focused on Metric Driven Verification of complex SoC's and their components.

Stewart currently works in the Cadence Research & Development organization as a developer of the Cadence Interconnect Workbench solutions.