Introduction to the QVN Protocol

I created a short introduction to the QVN protocol used with the QVN-400 plugin to NIC-400 and with the DMC-400 dynamic memory controller. This is a non-confidential introductory-level document for those seeking to understand how QVN works and what issues it can solve.

The Problem

Today’s SoCs often consist of dozens of masters and slaves, but typically most masters only target main memory (i.e. SDRAM), while the majority of slaves are only accessed by a very limited number of masters, primarily the CPU(s). It’s common for a large number of masters to contend for access to main memory and for the memory system to become a key bottleneck in the system.

QoS regulation and prioritization systems attempt to regulate traffic flow based on the requirements of the masters, e.g. bandwidth or latency targets and the capability of the memory system. Memory controllers typically contain a transaction queue and can re-order transactions based on QoS priority, but in heavily congested systems the memory controller queue may saturate resulting in the controller stalling the interconnect and ultimately creating back-pressure on masters.

This can cause blocking in the interconnect and no matter what QoS schemes are employed, latency will be indeterminate and uncontrolled. As a result, high priority traffic may get blocked behind low priority traffic, and cannot make progress to enter the memory controller queue where it could be prioritized appropriately. It would be desirable to enable traffic to flow uninterrupted from the master through the interconnect to the memory controller queue, where it can be prioritized accordingly.