By William Orme, Strategic Marketing Manager, Arm and Nick Heaton, Distinguished Engineer, Cadence
This is Part 1 of a 4 part series. Links below
The evolution of today’s system-on-chip (SoC) devices from uni-processor systems to heterogeneous multi-processor designs has added a significant burden to the SoC designer’s job. Combining a multitude of configurable interconnect IPs, asynchronous bridges, memory management units and security hardware together with a complex configurable dynamic memory controller is a difficult task, and validating that this combination delivers the performance needed is a major challenge.
This four part blog describes a more systematic approach to measuring and validating the system performance of these types of systems and introduces new tools to make this systematic approach practically achievable.
Figure 1 illustrates how functions with real-time, maximum-latency requirements compete with high-bandwidth streaming traffic, along with CPUs that need minimum latency to reach optimum performance. Advanced system IP—the “glue” that provides the interconnect tying all of the major functional blocks together and connecting them to main memory—is required to help solve these competing requirements. Just as each system may have its own unique set of design challenges, system IP is, by its nature, highly configurable, allowing the designer to choose the most optimal configuration for their design. Advanced system IP not only allows designers to select interconnect topologies but also places solutions such as hardware-managed cache coherency and dynamic end-to-end quality of service at their disposal.
Figure 1: Typical smart-phone traffic
The configuration options the designer chooses need to satisfy a multi-dimensional problem affecting the performance of each function as well as the physical size and power dissipation.
Figure 2: Typical Arm v8 big.LITTLE SoC core
Figure 2 which shows a typical Arm v8 big.LITTLE SoC core, typically these systems are composed using the Arm CoreLink System IP components.
The sophistication of these system IP components, is not only necessary to allow many functions to be integrated together, but also provides many choices to the designer. Finding the optimal configuration options that meet the requirements of a particular system, requires complementary design tools to enable the designer to rapidly explore and correlate trade-offs in performance, power, and area. The complexity of these classes of systems demands a systematic approach to validating their performance to ensure that performance bugs were not introduced by incorrect IP combinations or by incorrect static configuration. Additionally the validation engineer needs to define target use-cases for the SoC platform, run them and measure that the platform delivers the necessary performance under these dynamic scenarios.
This blog describes the challenges confronting the designer and proposes a two-step process to characterize the static performance limits of the system and to define use-cases to validate the dynamic performance of the system for its target applications. To ensure productivity in this space a new tool is described in part four that helps automate many of these tasks.
In part two of this series we will introduce the first step in this process, performance characterization.
How to Measure and Optimize the System Performance of a Smartphone RTL Design - Part 2
How to Measure and Optimize the System Performance of a Smartphone RTL Design - Part 3
How to Measure and Optimize the System Performance of a Smartphone RTL Design - Part 4
Cadence System Design and Verification