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SoC Design blog Cycle Accurate ARM Cortex-A53 and Cortex-A57 Models Support AArch64
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Cycle Accurate ARM Cortex-A53 and Cortex-A57 Models Support AArch64

Jason Andrews
Jason Andrews
May 1, 2014

We (The specified item was not found.) have just completed our first major release of 2014. It includes significant new content and many bug fixes to all products. Today, I would like to highlight the updated models of the ARM® Cortex™-A53 and Cortex-A57.

The latest ARM CPU models provide access to the ARMv8-A architecture. Since this is the first time Carbon models have supported the 64-bit architecture (also called AArch64 execution state), this is a great time to start learning some of the basics of the new architecture and get familiar with running and debugging software. The ARMv8 architecture is the largest change in the history of ARM!

It has been nearly 10 years since I wrote the book Co-Verification of Hardware and Software for ARM SoC Design. At that time, the ARM926EJ-S was a popular CPU for mobile devices (it’s now called a Classic Processor) and AMBA AHB was the main bus on many chips. Tremendous change over this 10 year period has brought us multi-core, multi-cluster systems utilizing Cortex-A7 and Cortex-A15 with ACE. Even with all of this change, certain things from 10 years ago still apply to an A15 system. For example, when address 0x10 appears on the bus and the simulation stops doing useful things I know it's a data abort and it probably means the software accessed a non-existent address in the system. This was the same in the ARM7TDMI as it is for the Cortex-A15. Now, the changes are more significant with the 64-bit ARM architecture (AArch64), and there is a lot to learn.

This is a great time to start learning the new architecture because many companies are currently working on new designs with A53 and A57 processors. One good place to start is to review some of the ARM presentations that are available. The ARMv8 Technology Preview is a good example of one I have looked at. Today, I’ll cover the basics of compiling and running bare metal software using the Carbon Performance Analysis Kit (CPAK) for the Cortex-A53.


Compiling Programs

The first thing to learn about v8 is how to compile programs. A new instruction set requires a new compiler, or at least a new compiler backend to generate the code. Many Carbon users will start with bare metal software programs and compile them using the ARM Compiler toolchain, also commonly called armcc. The programs in the CPAK were compiled with DS-5 version 5.17.1.

64-bit processors such as the A53 can also run in AArch32 state so this means a wide variety of choices are available when compiling a bare metal program. The --cpu flag is used to select the desired target architecture for armcc. A complete list is provided in the ARM Compiler Reference Guide.

Some of the programs that are included in the Carbon A53 CPAK use the --cpu=8-A.64.no_neon flag in the Makefile to select the target architecture. This CPAK is a good place to start to see the details of how to compile bare metal software.

In the Applications/ directory of the CPAK some examples are compiled for both AArch64 and AArch32. The Linux file command can be used to show the difference:

$ file DecrDataMP/decrDataMP.axf DecrDataMP_v8/decrDataMP_v8.axf

DecrDataMP/decrDataMP.axf:       ELF 32-bit LSB executable, ARM, version 1 (SYSV), statically linked, not stripped

DecrDataMP_v8/decrDataMP_v8.axf: ELF 64-bit LSB executable, version 1 (SYSV), statically linked, not stripped

It looks like the file command on my Ubuntu 13.10 machine doesn’t know the 64-bit program is for an ARM processor, but don't worry it will simulate fine.


Debugging Programs      

The most immediate difference when loading and debugging a 64-bit program is the General Purpose Registers are different. All of the registers are 64-bits wide and have Xn instead of Rn as the register names. Previously, R0 was 32-bits and now X0 is 64-bits. Below is a screenshot of the SoC Designer Plus register window for a program running on an A53 in AArch64 state. The registers shown are in the AArch64_Core group.

aarch64 regs

You will also notice there is a tab on the register window for the AArch32_Core group. These are the familiar 32-bit register values and correspond to the lower half of the AArch64_Core group. A screenshot from SoC Designer is shown below.

aarch32 regs

The ARM modeldebugger is an easy to use debugger which supports debugging 64-bit programs running on SoC Designer models. I like how the modeldebugger puts a space in the 64-bit register values.

md aarch64 regs

It's also useful to recognize the references to Wn registers as shown in the disassembly below. Some instructions work on 32-bit operands and will refer to the lower 32-bits of a 64-bit register using the Wn notation.

disass w regs

One benefit of AArch64 is the PC is easy to find, there is no need to know the PC is R15.

The other useful register for basic debugging is the stack pointer. The bare metal examples included in the A53 and A57 CPAKs run in exception level 3 (EL3) so the register holding the stack pointer is SP_EL3.

I hope this brief introduction about compiling and running bare metal software in AArch64 execution state using the newly updated Carbon CPAKs will help understand the basics and provide some motivation to learn more about working with 64-bit programs on ARM Cortex-A53 and Cortex-A57 models.

Jason Andrews

Anonymous
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