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Latest Blogs
  • The Flexible Approach to Adding Functional Safety to a CPU

    Naresh Menon
    Naresh Menon
    Find out more about Functional Safety with SoC designs and Software Test Libraries.
    • October 22, 2020
  • The Future of Safety in the Digital Cockpit

    Daniel Bernal
    Daniel Bernal
    Developed with support from Arm, CoreAVI brings to market a comprehensive suite of graphics and compute drivers and libraries that will be certifiable for use in ISO 26262 ASIL D applications, for Arm…
    • September 30, 2020
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Unanswered questions
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    ACE-Lite 0

    4793 views
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    by Ishan
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    httpd web server on stm32f407vg 0

    • STM32 F4
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    Started 5 months ago
    by rpj
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    Started 5 months ago
    by Ravi V.
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    BUSY transfer just before the last transfer in a burst by a AHB Master. 0

    6372 views
    1 reply
    Latest 6 months ago
    by Colin Campbell
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    AMBA AXI reset 0

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    • AXI
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    3 replies
    Latest 6 months ago
    by Colin Campbell
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Most viewed questions
  • Answered

    Arm alignment: all ARM processor requrie 4 bytes alignment for SP? 0

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    • Cortex-A
    • Cortex-A7
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    1 reply
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    by Yasuhiko Koumoto
  • Answered

    Hypervisor to experiment +1

    • AArch64
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    2265 views
    3 replies
    Latest over 5 years ago
    by Jerome Decamps - 杜尚杰
  • Answered

    Can I place the System MMU (SMMU-400) before the DRAM Memory Controller (DMC-400)? 0

    • Cortex-A15
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    • CoreLink MMU-400 System Memory Management Unit
    • Cortex-A
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    1 reply
    Latest over 6 years ago
    by Leah Schuth
  • Answered

    AHB HREADY low not after address phase +1

    • AMBA
    • System Architecture
    • Bus Architecture
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    2302 views
    1 reply
    Latest over 4 years ago
    by Simon Craske
  • Answered

    Write to GICv2's GICD_ITARGETSR -- wait for changes to take effects +2

    • Generic Interrupt Controller (GIC)
    2389 views
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    Latest over 4 years ago
    by Olivier Delande
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