Arm Community
Arm Community
  • Site
  • User
  • Site
  • Search
  • User
  • Groups
    • Arm Research
    • DesignStart
    • Education Hub
    • Graphics and Gaming
    • High Performance Computing
    • Innovation
    • Multimedia
    • Open Source Software and Platforms
    • Physical
    • Processors
    • Security
    • System
    • Software Tools
    • TrustZone for Armv8-M
    • 中文社区
  • Blog
    • Artificial Intelligence
    • Automotive
    • Healthcare
    • HPC
    • Infrastructure
    • Innovation
    • Internet of Things
    • Machine Learning
    • Mobile
    • Smart Homes
    • Wearables
  • Forums
    • All developer forums
    • IP Product forums
    • Tool & Software forums
    • Pelion IoT Platform
  • Activity
  • Support
    • Open a support case
    • Documentation
    • Downloads
    • Training
    • Arm Approved program
    • Arm Design Reviews
  • More
  • Cancel
Processors
  • Developer Community
  • IP Products
  • Processors
  • Jump...
  • Cancel
Processors
  • Blogs
  • Forums
  • Videos & Files
  • Help
  • Jump...
  • Cancel
  • New
  • All tags
  • coherency
  • Corelink
  • ACE
  • AMBA
  • bandwidth
  • Cache
  • CHI
  • CoreLink CCI-400
  • Corelink CCI-550
  • corelink_500_series
  • cortex_a73
  • Cortex-A
  • Cortex-A15
  • cortex-a50
  • Cortex-A53
  • Cortex-A57
  • Cortex-A7
  • dmc
  • gpu
  • interconnect
  • latency
  • Mali
  • memory_controller
  • mimir
  • performance
  • soc-interconnect
  • system_ip
  • Memory System is Key to User Experience with Cortex-A73 and Mali-G71

    Neil Parris
    Neil Parris

    By now you would have read the news about the latest ARM® Cortex®-A73 processor and Mali™-G71 GPU. These new processors allow for more performance in an ever thinner mobile device, and accelerate new use cases such as Virtual Reality …

    • over 4 years ago
    • Processors
    • Processors blog
  • Traffic Mixes in Networking Infrastructure - Base Transceiver Station (BTS) with CCN Interconnects

    Ian Forsyth
    Ian Forsyth

    Introduction

    ARM recently announced the next in the family of CCN (Cache Coherent Network) solutions. Specifically we introduced the CoreLink CCN-508. A quick recap – CoreLink CCN-508 is a cache coherent network providing support for up to 32 fully coherent…

    • over 6 years ago
    • Processors
    • Processors blog
  • Coherent Interconnect Technology Supports Exponential Data Flow Growth

    Ian Forsyth
    Ian Forsyth

    Introduction

    Recently I presented “Coherent Interconnect Technology Supports Exponential Data Flow Growth” at the Linley Processor conference in Santa Clara, CA where I announced a new ARM coherent interconnect product for enterprise applications, the…

    • over 6 years ago
    • Processors
    • Processors blog
  • 5 things you might not know about AMBA® 5 CHI

    William Orme
    William Orme

    ARM products in server and networking? Yes, it’s happening and AMBA® 5 CHI is a big part of making that happen. The AMBA 5 CHI protocol enables the latest ARMv8 architecture Cortex®-A50 series processors to work together in high-performance…

    • over 6 years ago
    • Processors
    • Processors blog
  • AMBA 4 ACE and Hardware Cache Coherency - Top 5 Questions

    Neil Parris
    Neil Parris

    I thought I'd post a short blog post about commonly asked questions on AMBA 4 ACE and system coherency.

    What does ACE mean?

    ACE is the "AXI Coherency Extensions" introduced with the AMBA 4 specification released in 2011. For those of you thinking "What…

    • over 6 years ago
    • Processors
    • Processors blog
  • big.LITTLE and AMBA 4 ACE keep your cache warm and avoid flushes

    Neil Parris
    Neil Parris

    Updated 29th October 2013


    High performance and power efficiency are critical to the latest mobile devices, and AMBA® 4 ACE™ is a fundamental technology supporting ARM's big.LITTLE processing. In case you missed the announcements, the big…

    • over 6 years ago
    • Processors
    • Processors blog
  • White paper: Optimizing Performance for an ARM Mobile Memory Subsystem

    Ashwin Matta
    Ashwin Matta

    Introduction

    Contemporary mobile platform SoCs impose intense traffic management demands on the memory subsystem. An intelligent memory controller design comprehends the fundamental memory streaming requirements of a mobile SoC and provides the necessary…

    • DMC Performance Optimization for Mobile Memory Subsystem.pdf
    • over 4 years ago
    • Processors
    • Processors blog
  • View related content from anywhere
  • More
  • Cancel