I've been reading books on the ARM Cortex-M architecture and as already mentioned in other post, all the books are consistent in saying that the PC points four bytes (Thumb Instruction Set) forward due to Pipeline (prefetch).
Did some testing with…
Background I'm working part-time on a Cortex M0+ based SoC converting a very processor-intensive section of C++ code (inner-loop executed 10s of 1000s of times a second & compiles to over 400 instructions using GNU O3) and after almost 3 months of work…
I want to store the value of Program Counter(pc) to a memory location.
I did this,
LDR R1, =[0x20000000]
STR R15, [R1,#0]
I got an error saying, "Error: r15(pc) not allowed here -- `str R15,[R1,#0]'.
How should I get over this error?
Cannot configure interupts of TIM6 on stm32f103 board
Does my NVIC configuration wrong?
Code:
@ stm32f103 timer & interrupt test by laper_s (from 2019-02-02) .thumb .cpu cortex-m3 .syntax unified .word 0x20005000 .word start + 1 b start…
In this blog I take a close look at the code size of ARM’s Thumb instruction set against the microMIPS32 instruction set, as used in the microAptiv processor family. More specifically I look at recent claims that microMIPS32 has 17%-30% better code…