So I'm working with QEMU and AArch64 mode and using the MMU. I've succesfully mapped 4K blocks, but I'm having trouble mapping 2M blocks. My configuration is such that the L1 entries are 1GB blocks, L2 entries are 2M blocks, and L3 entries are 4K, or…
Hi all - I'm trying to understand stage 1 translation.
Assuming that the translation is starting at level 2, how do you determine the number of page table entries in the level 2 table? The documnetation says it can have up to 512 for 4kb granule size…
Hi ARM folks, hoping someone can show me where I'm going wrong programming the MMU. The ESR_EL1 reports that it is a Permission fault, level 2. Here's what I'm trying to accomplish:
4GiB space, 4kiB granule flat identity mapped, divided like…
What I'm asking is ARM Architecture Reference Manual for ARMv8-A says in AArch32 there are two translation table formats:
On page G4-4726 (Issue B.b), there are various points listed that each…
Hi,
I have a question on ARM page table.
I am running a bare metal application on Cortex A72 and i have a failure with my application.
Upon debugging the failure, i found an address which is contributing the failure. our Bare metal application is responsible…
Dear experts,
working for Cortex-A55MP, EL1 in Aarch32, svc mode:
Both 2 level of table entry are attributed as (inner WB/WA, and outer WB/WA) and the MMU is set TTBR0 as…
I have a need at determining a page size, particularly for a Non-secure EL1, stage 1. I know of
__asm__ volatile ("at s1e1r, %0" : : "r" (buf)); __asm__ volatile ("mrs %0, PAR_EL1\n" : "=r" (par_el1));
Hello,
I am working on Cortex-A53 and using Cortex-A53 DSM Model in my design. We are getting Data Abort exception on a read to ROM address and ESR_EL3 register showing its a DECERR External error. MMU and Cache both are not enabled at this point where…
The ARM720T user manual mentions small and large pages. Since the ARM 720T requires a 64KB page table entry to be duplicated 16 times in the page table, why not place 16 small page (4KB) entries to mimic a 64KB page entry instead of using a large page…
From the TRM of the Cortex A9 we can read in section 7.4.3 Cortex-A9 behavior for Normal Memory Cacheable memory regions:
SCTLR.C=1 The Cortex-A9 Data Cache is enabled. Some Cacheable accesses are still treatedas Non-Cacheable:• all pages marked as Write…
SCTLR.C=1 The Cortex-A9 Data Cache is enabled. Some Cacheable accesses are still treated
as Non-Cacheable:
• all pages marked as Write…
Hi !
In order to call some functionality hard-coded in my board ROM (HAB from NXP i.MX6 board), I need to shut down the MMU: the ROM is not position independent. In particular, it is not always possible to map it and the devices correctly due to restriction…
Hello All,
Good Morning!
I am working on Cortex m4.
I have read following about hard fault ,
"Bus Fault: detects memory access errors on instruction fetch, data read/write, interrupt vector fetch, and register stacking (save/restore) on interrupt (entry/exit…
Hi Forum,
Why Cortex-R series is real time oriented than other ISA(ARM/others) ?
Is there a list of all the points and comparison with ARM Cortex-A ?
Why we can not make Cortex-A to suite for real time, which brings to think of Cortex-R ?
I am trying to understand…
What is different between AF & AP? I understand AP = permission access as read/write/readonly/no access but what is AF?
ARM V7 document states: "In ARMv7-A short descriptors only be used at EL0 and EL1 stage 1 translations. They cannot, therefore, be used by hypervisors or Secure monitor code."
Why stage2/hypervisors/secure monitor cannot use short descriptors…
I would like to know how to read the translation table info for A9 from embedded Linux.
In freeRTOS I have translation_table.S but I do not find anything similar for ARM architecure in linux kernel.
Should I just dump TTBR0/TTBR1 registers…
I am working on an Arria10 SoC which has dual ARM Cortex-A9 MPCore. And I work on bare-metal environment with Intel SoCFPGA’s hardware library(HwLib).
On the shared SDRAM, I am planning to have dedicated memory regions for each core, and a shared…
Hello there,
I want to enable MMU and Cache to improve the performance of my arm cortex-A5 core.
I have gone through the Reference manual of arm cortex a5 and found the below step to enable mmu and cache
Steps :
1.Disable cache, branch predictors
2. Invalidate…
Can anyone give some points as to how to design simple memory protection model, of standalone OS application composed tasks, each has its own region/section with attributes such as read only, write only, shared memory etc.
I mean, when a region…
I'm porting our armv7a-short descriptor OS to LPAE and aarch64. In the short descriptor MMU, the "NS" bit can only be found in the first level of the MMU (I'll call it the SECTION level), meaning that only a single page cannot be tagged as NS, a whole…
I'm developing a custom bootloader for NXP i.MX6 DualLite (ARM Cortex A9).
In this bootloader, I need to initialize ~50 MB of RAM to Zeros, this part executes really fast after enabling Caches, MMU and Program Prediction.
What I need is to know…
When MMU is enabled, and a undefined abort exception is triggered, are we sure that the address stored in the `lr` / `elr_elx` registers is actually mapped by the MMU, or should I check that before trying to access the address ?
Best,
V.
hi,
on a cortex a53, I would like to get the best of both worlds. Having dcache enabled but no page walk in case of a miss.
I want no memory protection because we manage the whole system ( kind of baremetal processes)
Is there a way to tell the mmu controller…
Hi ARM experts,
I have a problem in using armv8 mmu in bare-metal system:
When using the 4KB translation granule, level 1 table which use D_Block convert VA to 1GB region PA.
In Armv8 ARM page D4-1744, table lookup starts at level 0.
Is the Level 0 table…
Hello all,I want to improve VM operation in AArch64 port of FreeBSD but I stuck on following problem.The FreeBSD VM subsystem is capable to map various *kernel* objects by using superpage (higher order) mapping. But in lifecycle of these objects (because…