I am working on an Arria10 SoC which has dual ARM Cortex-A9 MPCore. And I work on bare-metal environment with Intel SoCFPGA’s hardware library(HwLib).

On the shared SDRAM, I am planning to have dedicated memory regions for each core, and a shared…

Hello,

I have been reading and searching for some time and have learned a lot about the MPU on an ARMv7-a. I am attempting to use the Unified Region Base/Size registers to both limit memory access, but also have the "Base" value added to memory references…