• Data Abort Exception in A53

    Hello,

    I am working on Cortex-A53  and using Cortex-A53 DSM Model in my design. We are getting Data Abort exception on a read to ROM address and ESR_EL3 register showing its a DECERR External error. MMU and Cache both are not enabled at this point where…

  • Cortex A9 single core

    From the TRM of the Cortex A9 we can read in section 7.4.3 Cortex-A9 behavior for Normal Memory Cacheable memory regions:

    SCTLR.C=1 The Cortex-A9 Data Cache is enabled. Some Cacheable accesses are still treated

    as Non-Cacheable:

    • all pages marked as Write…

  • Why Cortex-R series is real time oriented ?

    Hi Forum,

    Why Cortex-R series is real time oriented than other ISA(ARM/others) ?

    Is there a list of all the points and comparison with ARM Cortex-A ?

    Why we can not make Cortex-A to suite for real time, which brings to think of Cortex-R ?

    I am trying to understand…

  • dump MMU translation table for A9 in Linux

    Hello,

         I would like to know how to read the translation table info for A9  from embedded Linux.

         In freeRTOS I have translation_table.S but I do not find anything similar for ARM architecure in linux kernel.

         Should I just dump TTBR0/TTBR1 registers…

  • MMU initialization for an ARM multicore system

    I am working on an Arria10 SoC which has dual ARM Cortex-A9 MPCore. And I work on bare-metal environment with Intel SoCFPGA’s hardware library(HwLib).

    On the shared SDRAM, I am planning to have dedicated memory regions for each core, and a shared…

  • MMU and Cache configuration

    Hello there,

    I want to enable MMU and Cache to improve the performance of my arm cortex-A5 core.

    I have gone through the Reference manual of arm cortex a5 and found the below step to enable mmu and cache

    Steps :

    1.Disable cache, branch predictors

    2. Invalidate…

  • ARM Cortex A9 - Enabling/Disabling the Caches

    Hello,

    I'm developing a custom bootloader for NXP i.MX6 DualLite (ARM Cortex A9).

    In this bootloader, I need to initialize ~50 MB of RAM to Zeros, this part executes really fast after enabling Caches, MMU and Program Prediction.

    What I need is to know…

  • MMU: force identity mapping without pages?

    hi,

    on a cortex a53, I would like to get the best of both worlds. Having dcache enabled but no page walk in case of a miss.

    I want no memory protection because we manage the whole system ( kind of baremetal processes)

    Is there a way to tell the mmu controller…

  • ARMv8 mmu problem

    Hi ARM experts,

    I have a problem in using armv8 mmu in bare-metal system:

    When using the 4KB translation granule, level 1 table which use D_Block convert VA to 1GB region PA.

    In Armv8 ARM page D4-1744, table lookup starts at level 0.

    Is the Level 0 table…

  • Cortex-A5 and configuration for real time task

    Hello,

    in my recent design I have used a processor with Cortex-A5 core (it is SAMA5D27 from Microchip). There is one critical task which needs to be performed in real-time. Could you, please, give me a hint on how to configure the processor for that?

    …

  • Issues in Cortex A9 bareboard code if L2 cache controller registers are not mapped

    Hi

    I have written a bareboard code for i.MX6 (Cortex A9 Quad core). I am activating and using only one core.  Once I enable the MMU, code throws random exceptions. Both L1 and L2 caches are disabled. The interesting part is that if I just map the memory…

  • L2 Cache(Pl310) initialisation sequence

    Hi ,

    I would like to validate L2 cache memory using U-Boot code which running on cortex-A9 dual core.

    Here is my L2 Cache initialisation code , While Reading/Writing to DDR Memory location, I doesn't see any Drhit,Dwhit event count register gets updated…