• Arm64 Long Format Translation Table Walk

    Hi all - I'm trying to understand stage 1 translation.

    Assuming that the translation is starting at level 2, how do you determine the number of page table entries in the level 2 table? The documnetation says it can have up to 512 for 4kb granule size…

  • Permission fault, level 2 on MMU enable

    Hi ARM folks, hoping someone can show me where I'm going wrong programming the MMU. The ESR_EL1 reports that it is a Permission fault, level 2. Here's what I'm trying to accomplish:

    4GiB space, 4kiB granule flat identity mapped, divided like…

  • Why does Arm still support short descriptors?

    What I'm asking is ARM Architecture Reference Manual for ARMv8-A  says in AArch32 there are two translation table formats:

    • Short descriptors: 32 bit
    • Long descriptors: 64 bit

    On page G4-4726 (Issue B.b), there are various points listed that each…

  • determine a page size on armv8

    Hi,

    I have a need at determining a page size, particularly for a Non-secure EL1, stage 1. I know of 

    __asm__ volatile ("at s1e1r, %0" : : "r" (buf));    
__asm__ volatile ("mrs %0, PAR_EL1\n" : "=r" (par_el1));

    …

  • armv7a/armv8 : Undefined Abort Exception and MMU

    Hi !

    When MMU is enabled, and a undefined abort exception is triggered, are we sure that the address stored in the `lr` / `elr_elx` registers is actually mapped by the MMU, or should I check that before trying to access the address ?

    Best,

    V.

  • ARMv8 mmu problem

    Hi ARM experts,

    I have a problem in using armv8 mmu in bare-metal system:

    When using the 4KB translation granule, level 1 table which use D_Block convert VA to 1GB region PA.

    In Armv8 ARM page D4-1744, table lookup starts at level 0.

    Is the Level 0 table…

  • MMU - Permission Fault with EL1 access

    Hello everyone,

    I'm trying to wrap my head around the MMU configuration for Cortex A53 armv8 architecture (AArch64). Specifically, I'm programming for Raspberry Pi 3 (Bare Metal).

    I've successfully setup the page tables for two levels covering…

  • TTBR1 translation fault when using an identity mapping

    Hello everyone,

    I'm experimenting a bit with MMU after understanding its core principles. Specifically I can successfully enable it with an identity mapping for TTBR0 (no TTBR1) on a Raspberry Pi 3 (Cortex A-53, ARMv8 AArch64).

    The next step I wanted…

  • Enable MMU and d-cache on ARMv8 for u-boot

    Hi,
    This question is for MMU and d-cache. When I tried to enable MMU and d-cache for u-boot I ran into Synchronous Abort handler while writing to PCIe device registers which I mapped as uncached memory. The dump is shown below
    "Synchronous Abort" handler…