Howdy, I was trying to find some basic performance benchmarks for a couple of different ARM cores: The Arm 926EJ-S, Cortex A9, and the Cortex M7.
I am looking for primarily DMIPS (per MHz or a form that requires me scaling to my specific chip is fine…
I need the ARMv6-M Architecture Reference Manual and ebrising abaut the cortex m0
Hi, Coming from a games coder background, I always seek to find the very limits of what a CPU can do. Now we have PragmatIC and very cheap CPUs but much more importantly - vastly cheaper MROM (Mask ROM). With this in mind, I wanted to know how many registers…
AMBA spec states that 'Master can choose whether to terminate current burst or continue with burst in response to ERROR'.What does Cortex-M3/M4 do in response to ERROR? Does it continue with burst in response to ERROR in some special cases?
Hi,
I'm using the STM32 F407 (Cortex M4), and I am also only using assembly in uVision IDE. So far I have managed to setup a ISR for a pushbutton generated interrupt via GPIO. This all works, I get the ISR handler hit, but after I perform my ISR function…
Hi, All.
I want to start booting up a code in RAM starting with 0x1000 address in below circumstances. Please give me any advices for the below explanations.
My platform has one ROM and one RAM.
ROM and RAM both have their own F/W.
Core executes ROM codes…
This is in the context of the Cortex-M3 and PrimeCell uDMAC as implemented in the Texas Instruments CC2640R2F Bluetooth controller (I have gone through the TI support forums for this question but it seems that this is fully within the ARM IP domain…
Hey.
I read ARMv7-M Arch manual.
SHCSR register have SVCALLPENDED bit.
So that, It seem SVC is pendable.
But, 'Priority escalation' is written,
When the group priority of a pending synchronous fault or supervisor call is lower than or equal to…
Hello,
I need help with heap initialization using scatter file and C++ startup.
MCU is STM32F407VGT6 (Cortex-M4).
Compiler is ARM Compiler 6.7, C++14.
The problem is that all variables which I create dinamically on the heap have wrong addresses. My HEAP…
I have some assembly for Cortex M4 (Arm 7M Thumb), I want to enable an interrupt that is connected to a push button on an STM32 F407. It works, but for some reason when I enable the set enable register, the clear enable register also gets set ? Is…
Hi, I am trying to do file in DS-5 (evaluation version) using semihost, gettting errors (fopen returns -1). Is the eval version not able to do file IO?
Hi all,
I'm study Cortex-M4 recently, and try to use floating point calculation,
I read the book about that saying FPCA in control register will be set 1 after FPU work,
but I'm not sure that when will FPCA be changed after set 1, or it will never…
Dear All,
this is my first post and I hope I do not make any serious mistakes.
My question is regarding the use case of the cortex-m7 VFMA/VMLA instruction.
I am evaluating a polinomial for which the C compiler emits VFMA.F32 instructions. Out of curiosity…
I'm designing a MCU platform that is using ROM and RAM.
My boot up scenario is as follows.
First, ROM F/W is executed after power up(ROM F/W is excecuted only 1 time).
And then, core waits for until program counter jump flag goes high at the end of ROM…
We have a device which is used with NXP1115/303 MCU(cortex M0 core). Application doesn't do much, most of the time it sleeps in the deep power mode since the device is on 3V lithium batery. The system do a soft reset every 30sec. Reset is implemen…
I am using the KEIL MDK-5, assembly. The project compiles without some problems, but when i see the disassembly the assembler change the inmediate value
Assembler substitute one instruction for another
My code:
The instruction: SUBS R2,#0xC7
the assembler…
I need to change the Vector Table but I need it to be persistent through a reset, what I'm trying to do is set a vector table duplicate as a safety measurement for reprogramming the original vector table.
So far I being playing with the VTOR…
The G version has 410 pages!
However, the H version reduce to 133 pages!
It's like a big lost!
what's difference between the older and newer version?
I think it's the ARM job to tell the difference. It's hard and wasting time for the user to…
Cortex-M7 processors tends to be for the high performance applications. So why it doesn't support bit-banding if this has a lot of advantages to the code size and performance?
Hi guys, I am interested in exploring a scenario when Cortex M4 cpu performs a 16-bit static memory read when 32-bit memory is actually on the board.
The 16-bit memory chip is connected to lower half of the data bus, signals D0..D15 and there are two…
I have a question regarding BASEPRI, BASEPRI_MAX, and DMBs as they relate to both the V7-M and V7E-M architectures.
Let's say I have the following assembly,
// stuff mrs r0, BASEPRI msr BASEPRI_MAX, #3 // more stuff
Is it necessary to put a…
I am trying to use arm softcore along with my RTL in Kintex 7 board. What tool set is suggested? for both hardware and embedded development?
Hi everyone,
I wonder if there is a documentation that explain how to program efficiently on arm cortex-m and arm cortex-r platform?
I found "arm system developer's guide", but i worried it was too "old-fashion" because it only contained upto armv6..…
Hi, I am developing a fixed-point MP3 & ACELP decoder on an Arduino Due. I realize that bit-banding makes a RMW sequence atomic but I notice fields in the Due hardware are multi-bit fields. Is there an atomic way to alter multiple bits? I realize that…
The ARM Cortex-M4 Processor Technical Reference Manual states:
To minimize interrupt latency, the processor abandons any divide instruction to take any pending interrupt. On return from the interrupt handler, the processor restarts the divide instruction…