• System level Implementation of Generic Timer in Cortex A53

    Hi,

    Im new to ARM. Im learning generic timers in cortex a-53. I wanted to know whats the meaning of "system level implementation" of Generic Timer and "PE implementations" of the Generic Timer.  How is it different from Generic timer…

  • How memory mapping is done

    Hello, sorry if i posted in the wrong forum.

    I would like to know how memory mapping is done, that is to say which software/hardware component allow me to write for exemple into the address 0 of the flash memory in using the address 0x20000000 in my code…

  • Load / Store timings with different cache settings

    Hello,

    I am timing load and store instructions for baremetal program by stepping though execution using OpenOCD and using the PMU cycle counter with single cycle granularity. I am running the program on a single core of a Cortex-A9 on a Xilinix Zynq-7000…

  • Generic Timer in Cortex A-53

    1. What is the input & output of system counter? What is it's purpose? How to start/stop it?
    2. What is the input & output of Physical counter? What is it's purpose? How to start/stop it?
    3. What are the differences between Physical Counter &…
  • ARMv8: strongly ordered memory and exclusive access

    We are developing a bare metal secure OS on a NXP LS1043a board, with a Cortex A53 v8 core.

    While debugging some issue with DMA, I decided to switch all kernel mapping from Normal cacheable to Strongly ordered (Device-nGnRnE memory type) and then witness…

  • could anybody help me to write a bare metal startup code for LS1043A (ARM V8,A53)in 32bit(AARCH32)mode

    excuse me for my English!!!

    i want to write bare-metal startup code in 32-bit mode for LS1043A-Rdb.it is having V8 A53 core.

    i have bare-metal 32bit(AARCH32) code for xilinx processor(which is of V8,A53core).How much of that code is useful to write code…

  • help me to understand this assembly program for configuring MMU for ArmV8,A53.

    ******************************************************************************/
    /*****************************************************************************/
    /**
    * @file translation_table.s
    *
    * @addtogroup a53_32_boot_code
    * @{
    * <h2> translation_table…

  • about cortex-A72

    hello guys, can you tell me the number of execution units in Cortex-A72 and the number of clock cycles it takes per instruction?

    Thanks in advance

  • Using PMU on cortex-a9 CPU

    Folks,

    I am trying to run linux 'perf' on a new board with 2 ARM cortex-a9 CPUs. After compiling the kernel to include perf tool, i run 'perf stat true' and it returns valid stats. But when I run 'perf record' to profile my program, it doesn't record…

  • Could anybody tell me how to boot up a processor in AARCH32 bit mode in Arm V8 and A53 core?

    can you please tell me how to boot up a processor in 32 bit mode for Armv8, A53 core using baremetal code?

    how can i know it is booted in 32bit mode?

    Thanks.

  • Cortex-A53 Cache protection

    Hello all,

    The "Core Technical Reference Manual" specifies in chapter 8.2 the error reporting mechanism for all types of uncorrectable errors in the caches, except for L1 D-cache data (which is SEC-DED) and for L1 D-cache dirty (which is SED-SEC) triggered…

  • MMU: force identity mapping without pages?

    hi,

    on a cortex a53, I would like to get the best of both worlds. Having dcache enabled but no page walk in case of a miss.

    I want no memory protection because we manage the whole system ( kind of baremetal processes)

    Is there a way to tell the mmu controller…

  • Arm a53: Populate TLB without table walk?

    Hi,

    From a previous question I got that setting the EPDx bits from the TCR_ELx register to 1 will disable table walk.

    Good starting point. But, should I access the same memory location again, it won't be in the TLB cache.

    How to work around that?

  • ARMv8-A CurrentEL Register Definition

    Where is the register definition of the CurrentEL register ?. I cannot seem to find it in the ARMv8A programming model guide or the Cortex-A53 TRM.

    . How does the PSTATE bits map to CurrentEL ?

    I read somewhere that a CurrentEL value of 0x4 denotes EL1…

  • What ARMv8.x revision Cortex-A35 is?

    Hi,

    ARMv8-A specification mentions revisions and options. I cannot find Cortex-A35 adheres to which exact version: ARMv8.1, 8.2, 8.3? I want to know which of the extensions described in the generic ARMv8-A spec are really available in that core.

    Thanks…

  • Multi core L1 cache coherent

    Dear experts,

     I'm going to implement multi-core(4 cortex-a53) in my private OS. I have an issue which needs your confirmation.

    Q. When core0 invalidates the L1-cache and L2-cache at VADDR(Cached), Can other cores  get the right data at VADDR ?

    For…

  • indirect branches in ARMv8

    Please clarify that with me... With

    "The current Program Counter (PC) cannot be referred to by number as if part of
    the general register file and therefore cannot be used as the source or destination
    of arithmetic instructions, or as the base, index…

  • Cortex-A7 Generic Timer Clock and Operation

    Hi,

         I'm using NXP imx6ul-evk(single core cortex-a7 processor) and I'm trying to operate CPU at different frequencies(642MHz, 480MHz, 100MHz, 12MHz) and experiencing time drift on certain frequencies (Generic Timer's time lags Real Time), I'm using virtual…

  • Trustzone FIQ latency measurement When security extension is enabled

    Hello Guys,

    Please refer below attached image. as shown in this image i want to measure the different latencies in my Trustzone based application.

    Here is the list of measurements which i want to perform.   

    1) FIQ latency when RTOS runs and FIQ occurs …

  • GIC-400 controller virtual interrupt handling in VM and hypervisor

    Hi, I am new to ARM architecture and as of now exploring GIC Controller GIC-400 and using ARM Cortex a57.

    Sorry for asking very fundamental flow of interrupts handling GIC-Virtual extension

    Let assume a physical interrupts acknowledged by hypervisor in…

  • which register are dedicated for each MPCore in ARMv8-A architecture?

    Hi  Expert,
    I'm a beginner to ARMv8-A architecture MPcore and now studying A35 MPCore processor documents for low-level software developing.
    One question, when I read DDI0487C_a_armv8_arm and DEN0024A_v8_architecture_PG, from my understanding, there…
  • How to access the system control register?

    Hi all,

    I am trying to access the system control register in my ARM C program. The code (with heading 64 bit) I used is presented below. However I got the following error message during compilation.

    /tmp/cc7Dc236.s: Assembler messages:
    /tmp/cc7Dc236.s:31…

  • Information about ARM System control registers.

    Hi all,

    I noticed there are multiple system control registers in ARM.

    The SCTLR_EL1 , SCTLR_EL2 and SCTLR_EL3.

    I want to know, what do multiple such system controls registers represent??

    I am particularly interested in the A bit of the system control register…

  • Feature Comparison ARM v8 series

    Hi Experts,

    Please specify is there any document on the Cortex A series comparison sheet for the various properties.

    For example, Table 2.1 in the https://static.docs.arm.com/den0024/a/DEN0024A_v8_architecture_PG.pdf has details on A53 and A57. Likewise…

  • ARMv7-A: Cache maintenance operation by VA, performance

    Hi,

    according to this talk, cache maintenance should always be performed by VA and not by set/way except during boot or shutdown. However, invalidating/cleaning a block of data by VA requires a loop to run over the entire memory block (in steps equal…