• What's the single cycle Load-Use in ALU mean?(In Cortex-A7)

    What's the single cycle Load-Use in ALU mean?

    This is in the follow picture:

    CA7_detailpipeline.jpg

  • The cortex-A7's pipeline support dual-issue, so I want to ask what's the dual-issue mean?

    The cortex-A7's pipeline support dual-issue, so I want to ask what's the dual-issue mean?

    I find some answers say that dual-issue means that the cortex-A7 can issue two instructions per clock.

    But in the cortex-A7's pipeline diagraph, it has integer…

  • How does the BTIC(branch target instruction cache) works?

    in cortex-A series, most core has the BITC(branch target instruction cache). It is contained in the prefetch unit.

    Branch Target Instruction Cache

    The PFU also contains a four-entry deep Branch Target Instruction Cache

    (BTIC). Each entry stores up to two…

  • Is First-level table skippable? (VMSA)

    Hi forks. I am a newbie engineer for arm-processor and I have a question about VMSAv7-32.

    According to ARMv8 architecture manual, page 3592: arm processor can skip first level table if a first level table would contain only one entry..

    How arm processor…

  • How to learn ARM

    Hi everyone!!

    I am looking to work on some projects using ARM. I have completed a basic course on ARM M3/M4 (UT Austin 6.01x by Jon Valvano and Ramesh Yerraballi) online. Now, I want to learn advanced things, especially real-time applications. How should…

  • How to compare ACPI states (Sx, Cx) with ARM Cortex-A processor states (Standby, Retention, Power Down, Dormant Mode, Hotplug, Stop, Deep Sleep) ?

    Hello,

    I'm a student and I'm interested in how to compare ACPI Sleep States (Sx) and processor power states (Cx) with ARM Cortex-A states e.g. Standby, Retention, Power Down, Dormant Mode, Hotplug, Stop, Deep Sleep

    Thank you

  • Sampling/tracing memory addresses

    Is there any ARM tool that will sample or trace addresses of memory accesses for a processes?  And specifically for a Cortex A72-A.  It appears that there is support for this with the Statistical Profiling Extension or an Embedded Trace Macrocell, but the…

  • Cache lock down in ARM Cortex-A7

    I want to improve the performance of some game in our platform. I have heard of cache lock down feature to achieve performance improvement. Please suggest me how to use this feature in ARM Cortex-A7 for performance improvement.

  • Explain 8 stage pipeline of ARM Cortex a7?

    Brief explanation of each stage of ARM pipe-lining.  

    How many Neon pipeline stages are their?

    What is dual issue in ARM pipe-lining?

  • multi core programming

    hi 

     I have four functions and I am using cortex a7 processor. I want every core to execute one function. so to achieve this which registers and which manual and section should I refer too.

    i have placed one of my function say func1() at some address x…

  • Which is better of thees CPUs

    Which is better of thees CPUs:

    Cortex A53 octa core 1.5 ghz,

    Cortex A7 Allwinner T8 Eight core 2.0 ghz,

    Cortex A9 Quad-Core 1.8 ghz ?

  • Cortex A7 - Boot from SPI NOR vs Execution In Place (XIP)

    Hi folks,

    I've been working for years with ARM -M processors and I'm facing -A processors for the first time.

    I fell in love with Allwinner's V3S processor which is v7-A type.

    The datasheet says that the processor is able to boot from an external…

  • Different performance in HYP and SVC mode ARMv7A?

    I'm doing some testing on Exynos5422 SoC which implements big.LITTLE architecture (A7 + A15), I'm running bare metal application which starts in HYP mode. I haven't returned from HYP mode by accident and then software delay which I implemented by simple…

  • Trustzone FIQ latency measurement When security extension is enabled

    Hello Guys,

    Please refer below attached image. as shown in this image i want to measure the different latencies in my Trustzone based application.

    Here is the list of measurements which i want to perform.   

    1) FIQ latency when RTOS runs and FIQ occurs …

  • Quad-Core Cortex A7 / MSDOS comparability

    I just bought a Samsung SM-T560 (WiFi) SM-T561 (3G & WiFi) with a 1.3GHz: Quad-Core Cortex A7. I know nothing about processors but in searching the Internet I have found some applications that will allow Windows OS to run an Android system.

    Is the 

    …

  • ARM PMU access DRAM Event

    Hi, accorting to the reference manual of cortex A7 https://static.docs.arm.com/ddi0464/f/DDI0464.pdf

    pagina 243, what event number i neet to select to count all the DRAM access (read / write)?

  • GICv2 initialization for Non-Secure World

    Hi,

    Recently I am working on porting our Cortex A7 code that used to run in secure world to non-secure world for some reason. I got a problem when it came to GIC initialization.

    I noticed that in order to manipulate a certain interrupt settings in non-secure…

  • DMIPS calculation for application software on ARM Cortex A7

    Hi There,

    Having below queries : 

    1. We have developed communication protocol stack and ported it on
    ARM Cortex A7 processor. We wanted to know, how to calculate DMIPS for our software.

    2. What is the maximum DIMPS available on ARM Cortex A7?

    Thanks…

  • Square root calculation results. FPU logic of A15 and A7 CPUs on Odroid-XU3 board.

    Hello,

    I did experiments with Odroid XU3. I have noticed interesting effect of square root calculation.

    I have received unexpected results, during experiments with execution time of 50 million square root operations.

      double temp = 5.0;

  double…

  • L1 data cache and unified cache disabled in AMP mode for Cortex-a7

    Hello Guys,

    in my system ( multi core cortex- a7 ), I do not want to be in SMP mode that means it is AMP mode and i need to clear the ACTLR.SMP bit to be in AMP mode but the strange thing which i found though cortex-a7 MPCore TRM is that , those L1 data…

  • Non-Cacheable memory and DMA on armv7a

    Hi !

    Consider a micro-kernel (not Linux) where device drivers are userland applications (PL0).

    We would like to use DMA based device, like an Ethernet controller for example. To this mean, the micro kernel allocate some memory to the user application…

  • Cortex-A7 Generic Timer Clock and Operation

    Hi,

         I'm using NXP imx6ul-evk(single core cortex-a7 processor) and I'm trying to operate CPU at different frequencies(642MHz, 480MHz, 100MHz, 12MHz) and experiencing time drift on certain frequencies (Generic Timer's time lags Real Time), I'm using virtual…

  • Raspberry Pi 2 JTAG error on memory access

    Hi all,

    I am trying to connect to the RPi2 JTAG.

    I have the following setup

    - Raspberry Pi 2 running Raspbian 8.0 (Jessie)

    - OpenOCD 0.9.0 with a J-Link EDU connected to a Ubuntu system.

    I setup the GPIO in order to expose the JTAG interface and the…

  • Can't find many microprocessor manufacturers with Cortex-A7 architecture?

    My understanding is that ARM Cortex-A7 architecture was released after Cortex-A9 and improves features of previous versions. However, I have only found one manufacturer, NXP, that uses Cortex-A7 architecture in their processors. I am referring to manufacturers…

  • How to configure L2 cache in Cortex-A7

    Hi all,

    I am working on OrangePi board. The board configuration is,

    • Quad-Core ARM Cortex-A7, 1.6 GHz
    • 32 KB L1 I-Cache and 32 KB L1 D-Cache per core
    • 512 KB L2-Cache

    I have few queries related to Cache memory,

    1. How to disable L2 cache of Cortex-A7 in…