• How get ARMv7 cache size

    Hi everybody!!

    I have a question on how get cache size on ARM v7-A, more specifically on A9 (or A7 or A15).

    In accordance with the TRM at page 1529 I get the value from CSSIDR register and I compute the cache size. More precisely, I do cache size = num…

  • voltage levels for dvfs

    Hello,

    i was wondering if the voltage levels for dvfs states are fixed at the design time. For example for Cortex A7 or A15. Is this information available?

    Thank you.

  • Questions about Generic Timer in ARMv8

    When two clusters(Big/Little) exist in SoC, the timer can be used to support Synchronization between two clusters.

    But How to understand "Synchronization", anybody can tell me some typical application context? I am really confused......

    And, if…

  • Where can I find the docments about how the ARM cortex-A series pipeline works?

    Where can I find the docments about how the ARM cortex-A series pipeline works?

    Such as the first step of the pipeline do what and the second step of the pipeline do what, and also the Cortex-A series has different pipelines(such as cortex-A7 is different…

  • What's the cortex-A7 pipeline's in-order and cortex-A15 pipeline's out-of-order mean?

    What's the cortex-A7 pipeline's in-order and cortex-A15 pipeline's out-of-order mean?

    In ARM's white paper(about the cortex-A7 and cortex-A15) says as follow:

    I want ask the in-order and out-of-order mean what?

  • Cortex-A7 pipeline is non-symmetric, what does this attribute mean?

    Cortex-A7 pipeline is non-symmetric, what does this attribute mean?

    My understand is that cortex-A7 pipeline's five entries does not have the same two, in the contrary, the cortex-A15 have the two entries are the same.

    ca7pipeline.PNGca15pipeline.PNG

  • Is First-level table skippable? (VMSA)

    Hi forks. I am a newbie engineer for arm-processor and I have a question about VMSAv7-32.

    According to ARMv8 architecture manual, page 3592: arm processor can skip first level table if a first level table would contain only one entry..

    How arm processor…

  • Different performance in HYP and SVC mode ARMv7A?

    I'm doing some testing on Exynos5422 SoC which implements big.LITTLE architecture (A7 + A15), I'm running bare metal application which starts in HYP mode. I haven't returned from HYP mode by accident and then software delay which I implemented by simple…

  • Square root calculation results. FPU logic of A15 and A7 CPUs on Odroid-XU3 board.

    Hello,

    I did experiments with Odroid XU3. I have noticed interesting effect of square root calculation.

    I have received unexpected results, during experiments with execution time of 50 million square root operations.

      double temp = 5.0;

  double…

  • A Walk Through the Cortex-A Mobile Roadmap

    Chinese Version中文版

    Introduction

    The ARM Cortex-A mobile application processor product line spans several generations and three main product tiers. Developers and SoC designers experienced with one or more of the newer ARM ARM Processors benefit from an…

  • High efficiency, midrange or high performance Cortex-A - What is the difference?

    A question that I am asked many times is – what is the fundamental difference between the high efficiency, mid range and the high performance application processors in the ARM Cortex family?

    The simple answer to this is – the power budget…

  • AMBA 4 ACE and Hardware Cache Coherency - Top 5 Questions

    I thought I'd post a short blog post about commonly asked questions on AMBA 4 ACE and system coherency.

    What does ACE mean?

    ACE is the "AXI Coherency Extensions" introduced with the AMBA 4 specification released in 2011. For those of you thinking "What…

  • big.LITTLE and AMBA 4 ACE keep your cache warm and avoid flushes

    Updated 29th October 2013


    High performance and power efficiency are critical to the latest mobile devices, and AMBA® 4 ACE™ is a fundamental technology supporting ARM's big.LITTLE processing. In case you missed the announcements, the big…

  • White Paper - Enabling Mobile Innovation with the Cortex-A7 Processor

    An excellent whitepaper that describes the features of Cortex-A7 and applications of this little processor.

    This white paper describes in detail the design choices considered including choice of feature set and performance level, and how its simplified…

    • Enabling_Mobile_Innovation_with_the_Cortex-A7_Processor.pdf

  • Multi-threading Technology and the Challenges of Meeting Performance and Power Consumption for Mobile Applications

    The implementation of multi-threading in multi-core processor systems is being heralded as a potential solution to the challenge of achieving ever-higher performance targets with strict limits on power consumption and heat dissipation. This article examines…

    • Multi-threading Technology and the Challenges of Meeting Performan.pdf