Hi everybody!!

I have a question on how get cache size on ARM v7-A, more specifically on A9 (or A7 or A15).

In accordance with the TRM at page 1529 I get the value from CSSIDR register and I compute the cache size. More precisely, I do cache size = num…

I'm thinking about using a cortex-a7 in "bare-metal" where I don't need much memory, so i'd like to avoid using external memory.

The CPU boots from an external 4MBytes SPI NOR FLASH chip.

It has 512 KBytes of L2 cache and 32 KBytes…

hi, experts:

I found ACTLR register definition is different between Cortex-A7 and Cortex-A9.

I have some questions about out cache concept in Cortex-A7.
1. Some program disable outer cache by setting ACTLR[1] = 0.

   So, is it only available with Cortex-A9…

What's the single cycle Load-Use in ALU mean?

This is in the follow picture:

in cortex-A series, most core has the BITC(branch target instruction cache). It is contained in the prefetch unit.

Branch Target Instruction Cache

The PFU also contains a four-entry deep Branch Target Instruction Cache

(BTIC). Each entry stores up to two…

Hi all,

I am working on OrangePi board. The board configuration is,

• Quad-Core ARM Cortex-A7, 1.6 GHz
• 32 KB L1 I-Cache and 32 KB L1 D-Cache per core
• 512 KB L2-Cache

I have few queries related to Cache memory,

1. How to disable L2 cache of Cortex-A7 in…

In ARM Cortex-A7 platform which includes L1 and L2 level caches，I start cache setup flow as follows:

     1. Enable SMP bit and disable MMU.

     2. Disable I cache in L1, and invalidate it , then enable it.

     3…