• Data Abort Exception in A53

    Hello,

    I am working on Cortex-A53  and using Cortex-A53 DSM Model in my design. We are getting Data Abort exception on a read to ROM address and ESR_EL3 register showing its a DECERR External error. MMU and Cache both are not enabled at this point where…

  • MMU: force identity mapping without pages?

    hi,

    on a cortex a53, I would like to get the best of both worlds. Having dcache enabled but no page walk in case of a miss.

    I want no memory protection because we manage the whole system ( kind of baremetal processes)

    Is there a way to tell the mmu controller…

  • MMU - Permission Fault with EL1 access

    Hello everyone,

    I'm trying to wrap my head around the MMU configuration for Cortex A53 armv8 architecture (AArch64). Specifically, I'm programming for Raspberry Pi 3 (Bare Metal).

    I've successfully setup the page tables for two levels covering…

  • TTBR1 translation fault when using an identity mapping

    Hello everyone,

    I'm experimenting a bit with MMU after understanding its core principles. Specifically I can successfully enable it with an identity mapping for TTBR0 (no TTBR1) on a Raspberry Pi 3 (Cortex A-53, ARMv8 AArch64).

    The next step I wanted…