• Trustzone and Hardware virtualization support

    Hello,

    I am looking for a development board that has an open Trustzone and hardware virtualization support. Do the Juno boards support this?

    Looking around the ARM A72/57/53 chips all support Arm Trustzone and have hardware virtualization support, however…

  • Power Management Options in Cortex A

    Hi Experts,

    Whether the ARM provides the power management controller inbuilt in the cortex A5x processors or it provides signal pins suitable for easy integration with the power management controllers ?

  • CPUID information about ARMv8 core

    Hi experts,

    I want to know if there are CPUIDs information in CHI interface about IP A53/57 Mpcore? and can CCN504 transfer the CPUIDs to Slave device? for example, AXI_USER？

    Thanks.

  • If non-secure world pass to virtual address (allocated by malloc or mmap) and ttbr value, how to find valid physical address in secure-world

    First sorry my english writing level. :-)

    In non-secure world using android system(linux kernel).

    I use big.little core Cortex-A53, Cortex-A57

    I was tested to 2case.

    previous stage.

         1. Linux allocation memory using(malloc or mmap)

    …

  • Does CCI-400 guarantees cache coherency between secure and non-secure worlds?

    Hi Experts,

    I'm developing some kind of Secure OS on A57/53 big.LITTLE SoC.

    While multi-core testing, I'm facing some wired problem on my world shared memory mechanism.

    When I run world shared memory test on a single core (using affinity), it works…

  • Why linux set memory as inner shareable in multi-cluster ARMv8 cores?

    Hi, 

    I have board with two clusters, one has 4*A57 cores, and the other has 4*A53 cores.

    The A57 cluster has its own L1 and L2 cache, A53 cluster also has its own L1 and L2 cache. Between the clusters there is a CCI.

    There is no L3 cache. So the memory…

  • Armv8 Memory Mapping

    I am looking to emulate an Apple II and would like to specify some address ranges as being memory mapped so that any access would result in perhaps an interrupt that I am then able to handle and in which I can determine the memory address being accessed…

  • Using an external clock - experts only

    I'm looking to emulate a 6502 on the ARM but I would like to make it cycle accurate so I need some way to interface to an external clock. I can't rely on an internal clock as there are external components that will rely on the external clock as well and…

  • Processor Modes in cortex-A57

    Hi,

    I have done some basic assembly in Armv7-A processors (cortex A9). The version of ARM supports modes like User, sys, SVC etc. Does the ARMv8 also has the similar modes? Where can i find the details. Please point me to the documents if any.

    Regards…

  • How to measure program execution time in ARM Cortex-A53 processor?

    Hi,

    I was using following method to read clock in cortex-a15:

           static void readticks(unsigned int *result)

            {

                struct timeval t;…

  • Cortex-A72 and Cortex-A5x series boards

    Hi Experts,

    Is there any sample development boards available on Cortex-A72/5x series ?

    Regards,

    Techguyz

  • Motherboard provider with Cortex-A53 or ARM Cortex-A57

    Hello,

    I want to experiment with a storage solution ARM based. Is there any provider actually selling dev kits or consumer boards based on ARM Cortex-A53 or ARM Cortex-A57?

    Obviously the main requirement for purchase is the availability of SATA3 ports for…

  • ARM Shares Updated Cortex-A53/A57 Performance Expectations

    1.jpg

    With the first Cortex-A53 based SoCs due to ship in the coming months, and Cortex-A57 based designs to follow early next year, ARM gave us a quick update on performance expectations for both cores. Given the timing of both designs we'll see a combination…

  • A Walk Through the Cortex-A Mobile Roadmap

    Chinese Version中文版

    Introduction

    The ARM Cortex-A mobile application processor product line spans several generations and three main product tiers. Developers and SoC designers experienced with one or more of the newer ARM ARM Processors benefit from an…

  • High efficiency, midrange or high performance Cortex-A - What is the difference?

    A question that I am asked many times is – what is the fundamental difference between the high efficiency, mid range and the high performance application processors in the ARM Cortex family?

    The simple answer to this is – the power budget…

  • AMBA 4 ACE and Hardware Cache Coherency - Top 5 Questions

    I thought I'd post a short blog post about commonly asked questions on AMBA 4 ACE and system coherency.

    What does ACE mean?

    ACE is the "AXI Coherency Extensions" introduced with the AMBA 4 specification released in 2011. For those of you thinking "What…

  • ARMv8 Architecture, The whys & wherefores of AArch64 - 64-bit Applications

    It’s been a year since ARM announced the first details of the new ARMv8 architecture with its support for 64-bit virtual addressing. This comparatively early announcement allowed the architecture to be discussed publically, and more importantly…

  • big.LITTLE and AMBA 4 ACE keep your cache warm and avoid flushes

    Updated 29th October 2013


    High performance and power efficiency are critical to the latest mobile devices, and AMBA® 4 ACE™ is a fundamental technology supporting ARM's big.LITTLE processing. In case you missed the announcements, the big…

  • Porting to Arm 64-bit

    This white paper is an introduction to porting existing code to the A64 instruction set supported by Armv8-A processors like the Cortex-A53 and Cortex-A57 from Arm. It will also be useful for those writing new code for these platforms.

    Why 64-bit?

    Diagram of evolution of Arm architecture

    …
    • Porting to ARM 64-bit v4(2).pdf