• Does CCI-400 guarantees cache coherency between secure and non-secure worlds?

    Hi Experts,

    I'm developing some kind of Secure OS on A57/53 big.LITTLE SoC.

    While multi-core testing, I'm facing some wired problem on my world shared memory mechanism.

    When I run world shared memory test on a single core (using affinity), it works…

  • Share aarch64 page tables created by Linux with SMMU

    Hello!

    I am currently working on creating a shared virtual address space in Linux arm64 on a Xilinx Zynq Ultrascale+ board. In the future it should be possible to share pointers/addresses between the Cortex A53s and the FPGA utilizing the built in ARM…

  • 4 CES trends that could shape 2016

    The beginning of a year brings with it the potential of many new things; resolutions, good habits and of course the new gadgets that promise to change our lives at CES. Amidst the glitz of promises of longer, healthier and more fulfilling lives, the first…

  • AMBA 4 ACE and Hardware Cache Coherency - Top 5 Questions

    I thought I'd post a short blog post about commonly asked questions on AMBA 4 ACE and system coherency.

    What does ACE mean?

    ACE is the "AXI Coherency Extensions" introduced with the AMBA 4 specification released in 2011. For those of you thinking "What…

  • big.LITTLE and AMBA 4 ACE keep your cache warm and avoid flushes

    Updated 29th October 2013


    High performance and power efficiency are critical to the latest mobile devices, and AMBA® 4 ACE™ is a fundamental technology supporting ARM's big.LITTLE processing. In case you missed the announcements, the big…