Hi All,

a SMP architecture, like CA53-4core-mp, with a secure OS running at aa32 secure state.

how to implement a suspend/resume flow on a individual core?

TRM only mentions about how to clean cache and off-line from smp

But how to do a cache flush through…

excuse me for my English!!!

i want to write bare-metal startup code in 32-bit mode for LS1043A-Rdb.it is having V8 A53 core.

i have bare-metal 32bit(AARCH32) code for xilinx processor(which is of V8,A53core).How much of that code is useful to write code…

******************************************************************************/
/*****************************************************************************/
/**
* @file translation_table.s
*
* @addtogroup a53_32_boot_code
* @{
* <h2> translation_table…

can you please tell me how to boot up a processor in 32 bit mode for Armv8, A53 core using baremetal code?

how can i know it is booted in 32bit mode?

Thanks.

Hi all,

I am trying to access the system control register in my ARM C program. The code (with heading 64 bit) I used is presented below. However I got the following error message during compilation.

/tmp/cc7Dc236.s: Assembler messages:
/tmp/cc7Dc236.s:31…

Hello experts,
I am working on a53 core in which I am not able to run string library functions like memset, memcpy etc. I have included the string.h library also but it is generation an exception. The same code works on the a15 core without any modification…

Since ARM caches are physically indexed is there any way to flush based on the PA? I know I can get the set, but what about the way? If I am flushing from L1 would I have to flush all ways in L1 and then L2 assuming there is no L3 to get to system memory…