• A9 Code after vector table

    I am implementing a small OS as a university project in a A9 chip (a Xilinx Zynq). I am using trustzone to implement some features and I want to pass through SVC calls from user mode directly to monitor, so I issue an SMC in my SVC handler. Here it is…

  • What's the relationship between exclusive access and memory cacheable in Cortex A53?

    Hello community and experts,

             I am doing an experiment on Cortex-A53 which executes some exclusive access instructions such as 'ldaxr'.

             When I config memory to Normal type+cacheable, 'ldaxr' can execute well. But if I config memory to Normal…

  • Can Cortex-A53 l2 cache be controlled seperatly?

    Hi Experts,

        I'm researching Cortex-A53 cache.

       Can Cortex-a53 l2cache be enable/disable independently? 

       Is it possible to only enable l1 cache and disable l2cache?

       Does cortex-a53 support l2cache lock function?

       Thanks for your attention!

    Best…

  • ARMv7 CortexA9 Cache Policy - No allocate ?

    I was wondering if it would be possible to configure cache policy in the page table entry (short descriptor format) in such a way that the cache is used only if the data already exists in the cache? A kind of write-through / "no-allocate" policy?…

  • Using an external clock - experts only

    I'm looking to emulate a 6502 on the ARM but I would like to make it cycle accurate so I need some way to interface to an external clock. I can't rely on an internal clock as there are external components that will rely on the external clock as well and…

  • A8: Keeping Cache-enabled and MMU-disabled

    Hi all,

    A Question about the A8 processor.

    If I enable the L1 and L2 caches, I see a performance boost even if the MMU is disabled. I was under the impression that the MMU is required to be enabled to use the Cache. I also do not see any errors or mismatches…

  • L2 cache with cortex-A8

    Hello,

    Can I assume that with cortex A8 cache invalidate/flush is used only with L1 ?
    I have some 2 implementation of this routines, one is called L1 and the other L2C-310.

    I am just not sure if using L1 will be good enough, or is it that cortex a8 internal…

  • ARM Cortex A8 L2 Cache Flush Invalidate

    Hi,

    I am working on DM37xevm platform and already invalidate the L2 cache (256KB) using the code

    asm volatile moveq r12, #0x1");                                                  …

  • Cache Allocation Technology

    Hi guys,

    I have a question regarding "Cache allocation technology" that is present in Broadwell processors of Intel. Does ARM (aarch32/aarch64) support similar way of partitioning the LLC for a process to access?

  • Intercore interrupts on a53 between EL1 and EL3

    We are working on Xilinx MPSOC which has 4 A53 cores, We are trying to run Linux(EL1) on 3 cores and Freertos(EL3) on 4th core. When software generated interrupts are raised from Linux , Freertos is not getting any interrupts. How to make interrupts work…

  • About watch point debug excption on Cortex-A53

    Now we are researching watch point function on A53. We simply write a driver, hook debug exception handler aml_watchpoint_handler instead of default watch point handler.

    In our watch point handler, we first disabled watch point control, then handle debug…

  • Cortex-A8 Pipelined cache maintenance

    Hi,

    I am new to the Cortex-A8,

    I would like to know what is the advantages of using "pipelined cache maintenance operations".

    "Auxiliary Control Register " has the  "Cache maintenance pipeline" bit enabled by default,
    is it recommended…

  • "CPSIE I"on an ARMv7A not changing the I bit in the CPSR register in USR mode - why?

    I'm using a CortexA8 and I can't seem to enable interrupts...! 

    I'm using a "CPSIE I" instruction, I can see that the compiler (GCC) is not optimizing my code out... I have to manually stop the program with a debugger and update the I bit myself…

  • Can Floating Point Unit(FPU) in cortexA9 processor raise an exception?

    Based on  ARM documents there is no exception ID for FPU (CortexA9) and just FPU instructions set exception flags in Floating-Point Status and Control Register (FPSCR). Is there a way to use these flags to raise an exception in the processor?

  • multi core programming

    hi 

     I have four functions and I am using cortex a7 processor. I want every core to execute one function. so to achieve this which registers and which manual and section should I refer too.

    i have placed one of my function say func1() at some address x…

  • Initial page table walk for secure/nonsecure accesses

    I have a basic concept question.  From what I read in the ARMv8 docs... there is an NS and NSTable bit in the page table entries themselves for the 2nd level and higher page table lookups.  So these can be used to block access ... I.e. NS access is attempting…

  • How to Write CP15 registers (CRn:C15) in Non-Secure mode

    Some of the Cortex-A8 registers like CP15 registers (CRn:C15) are writeable
    only in secure mode. How to write these registers when the CPU is in Non-Secure  mode?
    Please let me know if there is any reference example code on this.
    The Cortex-A8 manual mentions…

  • Precise abort vs synchronous abort in armv7

    I am new to arm architecture. I am reading exception handling from ARM cortex-A series programming guide. I have confusion about the technical difference between precise abort and synchronous abort or imprecise abort and synchronous abort. Are they refer…

  • SPI VIP

    how to implement the daisy chain concept in SPI vip?

  • SMP to suspend an individual core with security OS

    Hi All,

    a SMP architecture, like CA53-4core-mp, with a secure OS running at aa32 secure state.

    how to implement a suspend/resume flow on a individual core?

    TRM only mentions about how to clean cache and off-line from smp

    But how to do a cache flush through…

  • why inner attribute is affected by outer configuration?

    Hi expert:

    I am configuring a CortexA15 system. In the  LPAE page table entry, SH[1:0] is configured as 11, so this is a Inner Shareable field. Then I need to set MAIR0.attr0  which is used by stage 1 translation.  The problem is, my system behave differently…

  • Which is better of thees CPUs

    Which is better of thees CPUs:

    Cortex A53 octa core 1.5 ghz,

    Cortex A7 Allwinner T8 Eight core 2.0 ghz,

    Cortex A9 Quad-Core 1.8 ghz ?

  • Cortex-A15 MPCore: How to Enable Monitor Debug Mode

    Hi experts,

    I want to enable monitor debug mode for Cortex-A15 MPCore. I tried modifying DSCR[15] bit but watchpoint event still won't generate exception/abort. Core was in no-debug mode before modifying the DSCR (after power-on). I know I configured…

  • shareability attribute for armv8 cortex a-53

    Hi,

    I have a system with a multiple quad core clusters with Cortex A-53 and the CCN-512. L1 through L2 are integrated caches where L3 is an outer cache in 8xHN-F of the CCN512.

    My question is how should I interpret the shareability domain: inner, outer…

  • Cortex A7 - Boot from SPI NOR vs Execution In Place (XIP)

    Hi folks,

    I've been working for years with ARM -M processors and I'm facing -A processors for the first time.

    I fell in love with Allwinner's V3S processor which is v7-A type.

    The datasheet says that the processor is able to boot from an external…