Arm Community

General Feature of Cortex processors on cache coherency

techguyz

Hi Experts,
Is there any general feature available in the cortex processors to realize the cache lines by DMA through AXI ?
I found some features like CCI module available to provide this feature in multi-core environment. Other than that, is it possible…
- Answered
- over 5 years ago
- Processors
- Cortex-A / A-Profile forum
Extended System Coherency - Part 3 – Increasing Performance and Introducing CoreLink CCI-500

Neil Parris

Chinese Version 中文版：扩展系统一致性 - 第 3 部分 - 性能提升和 CoreLink CCI-500 简介

This week we announced the launch of a new suite of IP designed to enhance the premium mobile experience. A central part of this suite is the ARM CoreLink CCI-500 Cache Coherent Inter…
- Processors
- Processors blog
Extended System Coherency: Part 2 - Implementation, big.LITTLE, GPU Compute and Enterprise

Neil Parris

Chinese Version中文版：扩展系统一致性 - 第 2 部分 - 实施、big.LITTLE、GPU 计算和企业级应用

This is the second part of a series of blogs about hardware coherency. In the first blog I introduced the fundamentals of cache coherency. This part talks about the implementation of hardware…
- over 6 years ago
- Processors
- Processors blog
Extended System Coherency: Part 1 - Cache Coherency Fundamentals

Neil Parris

Chinese Version 中文版：扩展系统一致性 - 第 1 部分 - 缓存一致性基本信息

Introduction

The theme of TechCon 2013 was “Where intelligence connects” and in many ways hardware system coherency is an important part of connecting the intelligence of an SoC. This year I presented…
- over 6 years ago
- Processors
- Processors blog

General Feature of Cortex processors on cache coherency

Extended System Coherency - Part 3 – Increasing Performance and Introducing CoreLink CCI-500

Extended System Coherency: Part 2 - Implementation, big.LITTLE, GPU Compute and Enterprise

Extended System Coherency: Part 1 - Cache Coherency Fundamentals

Introduction