• Cortex A53 Bare metal booting have FIQ exception. How to debug?

    Hi

    I study coresight test with cortex A53 CPU.

    I get FIQ interrupt when I running helloworld test in ini_libc function. But I don't known why.

    I use gcc-linaro 4.9 toolchain : aarch64-none-elf-gcc  with glibc 2.14

    Set CPU config pin aa64naa32 to 1…

  • VMSAv8-64 and spinlock

    Hi,

    I'm trying to implement a spin-lock to synchronize the execution of all cores Cortex-A53 on my Xilinx-ZCU102 board, but I have some issues maybe due to a wrong configuration of the VMSA and cache coherence.

    I'm writing bare-metal code, without…