• Getting started with AMBA and AMBA AXI

    As you may be aware, far from being a misspelled fossilized tree resin, AMBA is a freely available open standard for the connection and management of functional blocks in a system-on-chip (SoC). Since the mid-90s, AMBA has been implemented by vendors…

  • 4-kbyte boundary space

    Note: This was originally posted on 22nd August 2012 at http://forums.arm.com

    Hi there,
    when I read AMBA AXI4 specification, the spec shows that "Bursts must not cross 4KB boundaries to prevent them from crossing boundaries between slaves and to limit the…

  • can we delay read and write transactions(axi4) by providing delay in register slice?

    Basically I want to provide delay of 15 clock cycles  for writing and reading through axi4 bus .Is it possible?

  • ACE-Lite Master and Slaves

    Hello Ashley,

          I have couple of basic doubts w.r.t ACE-Lite Slave.

          The AMBA spec for ACE-Lite says that " ACE-Lite is used by master components that do not have hardware coherent caches". But they can issue transactions…

  • Cortex-A53 backward compatible with AXI-4 interconnect

    Hi,

    The Cortex-A53 core supports either ACE or CHI as its master interface.  Assuming I don't need any of the coherent features introduced in the ACE specification, is there any functional problem if Cortex-A53 ACE interface is connected to an AXI-4 interconnect…

  • What's the difference between LDAXR and LDREX

    Hi experts:

    In armv8 specification, I have found two types of exclusive access instructions: LDAXR/STLXR and LDREX/STREX. I have some questions about these instructions:

    (1)  What's the difference between these exclusive access instructions?

    (2) Is…

  • AXI3 & AXI4 wrap burst length

    Hi,

    Was going through AXI spec.

    As per AXI spec:

    "AXI3 supports burst lengths of 1 to 16 transfers, for all burst types."

    "AXI4 extends burst length support for the INCR burst type to 1 to 256 transfers. Support for all other burst types in…

  • Can an ACE master have multiple write channels ?

    Can an ACE master have multiple write channels ?

    e.g. AW_0, AW_1, W_0, W_1, B_0, B_1, AR, R, AC, CR, CD

    Can this still be considered as an ACE-compliant component ?

  • Problems with  AXI4  write data channel

    Hello:

        Suppose there are 2 masters(master0 and master1) and 2 slaves(slave0 and slave1) for AXI4. As AXI4 protocol has removed WID signal for write data channel，When slave0 has received wvaild which is pulled up afte  slave0 has…

  • AXI4:what will happen if there is a AXI rd and wr concurrently for a same address for a particular slave??

    AXI4:what will happen if there is a AXI rd and wr concurrently for a same address for a particular slave??

  • Supported AXI transfers on Cortex-A9?

    Hi folks,

    The technical reference states that only a subset of possible AXI transactions are actually generated.

    This is described in http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0388f/Babiaggf.html

    What happens for this table if the master…

  • AXI4: Write-Alignemnent modes? Partial writing with write strobes possible?

    Hi guys,

    I have two questions related to the write-strobing in AXI4. Both examples work on a 32-bit bus.

    First consider an unaligned access on address 0x1.

    Can this access be created in 2 ways?

    1) Addr=0x0, Wrstrb=1110

    2) Addr=0x1, Wrstrb=0111

    In the second…

  • AXI4: Wider transactions than BUS width allowed?

    Hi AXI-experts,

    Does AX4 support burst sizes larger than the bus width?

    Narrow transactions are allowed, but do wider transactions also work?

    Best regards,

    Robert

  • AXI4: Unaligned read transactions

    Hi guys,

    I'm new to the AXI ecosystem.

    However, I have one question related to unaligned read transfers.


    Does AXI4 support unaligned read transfers although er are no strobe lines?

    If so, which data on the bus is written?

    To make it easier, discuss it…

  • Questions on AXI4

    I have bunch of questions related to AXI. Can someone help me by answering those?

    AxSize can be varied across multiple transactions?

    whose duty is to set byte strobe in a transfer? Is it the master which should generate byte strobes along with un-aligned…

  • Write interleaving with Multi-AXI master

    Hi,

    I have multiple questions related to multi-master AXI4 system. Eg: lets say we have 2 masters(m1,m2) and 2 slaves(s1,s2) and an interconnect.

    1) In parallel, Can i have transfers(burst) to m1->s1, m2->s2 on write data channels? A-data form M1,  B-data…

  • Reason for having decouple write address, data channels in AXI4

    Can someone explain me the advantage of having decouple write address, data channels in AXI4?

    In AXI3 with data interleaving we can have multiple masters sending data to various clients but in case of AXI4 we don't support interleaving so how decoupled…

  • About AXI4 address channel and data channel handshake sequence

    I wonder whether the read/write data channel handshake must occur or assert after the address channel handshake completed?

    For example the master device will wait ARREADY assert or ARVALID dessert, before assert the RREADY?

    Remark:

    Just now, I noticed that…

  • Support for pipelining flops in AXI

    Hi All,

    Does ARM support pipelining flops in between valid/ready signals?Can someone explain why its *not* possible?

    Thanks

  • MakeUnique Transaction (ACE protocol)

    Hi.,

    As we know that there is a MakeUnique transaction in ace protocol, can anyone tell me how we can initiate this transaction..? I mean what is the respective signal in AXI4/ACE that allows us to set a master to initiate this MakeUnique transaction.…

  • Are there any restrictions for the width of an address signal in an AXI4 interface?

    Hello,

    in the AXI4 specification I didn't find anything mentioned about width restrictions for the address signal. I'm currently trying to simulate a component which I wrote in VHDL which provides an AXI4 Slave interface. The BFM I'm using to simulate…

  • Need info AXI4- AxPROT

    Hello Everyone,

    Can someone explain the use cases of AxPROT? I am not fully clear on how to use these bits in a system. (So i would like to hear some use cases for this port)

    Also, Please provide some info on how to set AxPROT[1] (How the system will distinguish…

  • AXI Write data interleaving

    Hello Everyone,

    [This not specific to AXI3/4] Can someone give an example on how write data interleaving works? Is it used only when we have multi-master cases? or its possible with single-master cases also?

    In case if we have 2 burst transfers with A …

  • Address handshaking in AXI4

    Hi  there,

    I have question regarding handshaking in the AXI protocol.Currently i am designing  decorder for AXI4-Lite master .

    While doing the write adress  transaction, AWVALID  depends upon write enable.AWVALID is high when write enable signal…

  • Address decoding in AXI4 interconnect

    Hi, anybody explain how data  is routed in interconnect? As stated in AXI4 spec, only start address issued from master,then how it is done in case of burst transaction? Please Explain how this is done.