• Why do we have to send HMASTLOCK signal to the slave?

    In AHB-Lite cases, every transfer starts with address phase with signals from master.

    And also in multi-master cases, arbiter decides with whether it can GRANT bus access to other masters or not.

    So, I think it's fine to only let masters or arbiters to…

  • AMBA AHB SLAVE MULTIPLE SPLIT RESPONSES TO SINGLE MASTER

    Can the AMBA AHB Slave give multiple SPLIT response again to the AHB Master that has been given SPLIT response before and after updating hsplit signal for that Master by the Slave?

  • why AHB has two disparate data bus instead of one Bus for write/read?

    Hello,

    with reference to the subject above,

    in ahb spec.,there are both HRDATA and HWDATA buses.

    However,i can't figure out any possible scenario to meet the necessary of design instead of using same data bus.

    Hope someone can give some comment,thanks…

  • Memory controller for AHB, dual (or multi) channel

    Hi, I am looking for a memory controller for AHB, dual (or multi) channel.

    I found one in the ARM site but for AXI.

    Thank you

  • AMBA AHB5 : Stable Between Clock Question

    Hi All,

    I have a question on AMBA5 AHB feature : Stable_between_Clock property

    The AMBA5 AHB Specification describes:

    Signals that are described as being stable are required to remain at the same value when sampled at different rising clock edges in an…

  • In AHB, can i program HSPLITx signal from slave sequence

    Hi,

        I have a scenario like 2masters firing write or read burst to different slave.

         M1 ---> S1 (Slave S1 performs SPLIT response for any transfer of the burst )

         M2 ---> S2 (Slave S2 performs SPLIT response…

  • AMBA AHB

    Hi ,

    In AHB specs, There is one note as below.

    Note

    Every slave must have a predetermined maximum number of wait states that it will insert before it backs off the bus, in order to allow the calculation of the latency of accessing the bus. It is recommended…

  • In AMBA AHB, If EBT(early burst termination) is happened in address phase of a transfer then it's data phase will be driven or not?

    Hi,

       I have a question on AMBA AHB, Let us assume we are firing INCR4 burst from master M1.

      Let us assume  EBT is happened during 2nd transfer address phase of INCR4 burst (i.e Master M1 lost its grant without driving of its data phase and…

  • About AHB5 protection control signals

    In AHB5, we have extended memory bits as [6:4] hprot. Previously we have [3:0] hprot. For implementation purpose, i treated [6:4] as a separate signal. This separate signal am qualifying based on some filter, just because not to consider for older AHB…

  • AMBA

    Hello....!!!

    Can anyone tell the minimum and maximum frequency or bandwidth on which AMBA AHB, APB, AXI and CHI and ACE can work successfully?

  • how can i design APB to AHB bridge ??

    i want to design a bridge between APB  and AHB in verilog

    my design consists of :

    1. control clock unit (ccu)   // using APB

    2. my DUT contains registers module & functional module  // using AHB

    3. tow memories (source memory and…

    • tb-dtc.v

  • Without the IDLE transfer between the bursts, can the arbiter change the master?

    I have a problem about AHB 2.0, the circumstance is:

    The master send two burst without IDLE transfer, and the HBURST is INCR.

    So the arbiter can’t predict when the burst finishes.

    And the sequence of the HTRANS is as below:

    | NONSEQ  | SEQ | SEQ | SEQ…

  • How hsel behaves in AHB?? Relation with HWRITE ,HWDATA,HRDATA

    I wanted to know the relation b/w HWRITE and HSEL

  • I am working on ahb bridge , I am trying to sample address when hready is high .

    I am trying verify the bridge...........

    I am working on ahb bridge , I am trying to sample address when hready is high .

                   is it correct or not ?

    Address is indepent of hready…

  • What does an AHB slave do after issuing an ERROR, if the master decides to carry out the remaining transfers of the burst?

    The spec simply states that a master may cancel a burst after receiving an ERROR response for one of its transfers or continue with the remaining transfers.

    The spec does not go on to state what the slave is supposed to do in that case though. Should it…

  • AMBA AHB TRANSFER CONTINUE AFTER ERROR RESPONSE

    Hello everyone,


    Please describe me the transfer continuation process after ERROR response from the slave.ERROR response.jpg

    As shown in the above figure at cycle T4 if MASTER identifies the ERROR response from the SLAVE. Now, if the MASTER wants to continue the current transfer…

  • TRANSFER CONTINUE AFTER ERROR RESPONSE FROM SLAVE

    Hello everyone,

    I want to understand the transfer continuation process from AHB MASTER during ERROR response from AHB SLAVE.

    As specified in the AMBA Specifications (Rev 2.0) IHI0011A_AMBA_SPEC.pdf section 3.9.4 page no 3-23 :

    3.9.4 Error response

    If a slave…

  • Significance of [MS] and [LS] in big-endian data bus in AHB5 Specification

    Hi,

    As indicated in few previous answers (Link Given below) on the big-endian, I believe that the big-endian type in AHB-Lite Spec is BE32. And further the AHB5 Spec added another type of big-endian as BE8. Hence, the active byte lanes for a 32-bit big…

  • CM4: Can processor halt itself by writing DHCSR

    Hello,

    As part of my diagnostic regime I wanted the diag to halt when completed.  It doesn't seem like it can.  It seems to keep running when I 

      CoreDebug->DHCSR = (0xA05FUL << CoreDebug_DHCSR_DBGKEY_Pos) |
                         CoreDebug_DHCSR_C_HALT_Msk…

  • How cortex-M4 handles data hazard situations in the pipeline?

    Hello to all,

    Since I am working on ARM Cortex-M4, I would like to know about the handling of the hazard situations (especially the RAW, WAR and WAW hazard situations) in the pipeline.

    Is the processor also use the method of "Forwarding" in order to handle…

  • How does memory work in cortex M3?

    Hi 

    Now I'm trying to understand about memories in the Cortex design kit.

    I came across memory address map of cortex M3 when I googling as the below.

    In the image, left one is an AHB memory map, and right one is STM32F103's memory map.

    As you…

  • Cortex-M1 on Actel - how to start?

    Hello ARM Community,

    some time ago I started with Cortex-M1 core on Actel Proasic3L FPGA. I don't have much experience, but I have development board without working example:) I tried to follow Actel's tutorials and create simple LED blinking application…

  • Does Cortex-M3/M4 continue with burst in response to ERROR?

    AMBA spec states that 'Master can choose whether to terminate current burst or continue with burst in response to ERROR'.
    What does Cortex-M3/M4 do in response to ERROR? Does it continue with burst in response to ERROR in some special cases?

  • single-copy atomicity question for AHB5

    Hi all~

    I have some questions about AHB5 specification

    1.If CPU(or another slave) is in 32-bit single-copy atomic group, can I only write/read a byte to it ? (HWDATA/HRDATA is 32bit-width, HBUST=SINGLE, HSIZE='b000)

    2.What is the description "…

  • What happens to upper half of 32-bit data bus when reading 16-bit chip?

    Hi guys, I am interested in exploring a scenario when Cortex M4 cpu performs a 16-bit static memory read when 32-bit memory is actually on the board.

    The 16-bit memory chip is connected to lower half of the data bus, signals D0..D15 and there are two…