• How to start boot up in the region of 0x1000 memory address (Cortex-M0)

    Hi, All.

    I want to start booting up a code in RAM starting with 0x1000 address in below circumstances. Please give me any advices for the below explanations.

    My platform has one ROM and one RAM.

    ROM and RAM both have their own F/W.

    Core executes ROM codes…

  • Cortex M3, PrimeCell uDMAC bus arbitration

    Hi,

    This is in the context of the Cortex-M3 and PrimeCell uDMAC as implemented in the Texas Instruments CC2640R2F Bluetooth controller (I have gone through the TI support forums for this question but it seems that this is fully within the ARM IP domain…

  • Is SVC pendable on cortex-m?

    Hey.

    I read ARMv7-M Arch manual.

    SHCSR register have SVCALLPENDED bit.

    So that, It seem SVC is pendable.

    But, 'Priority escalation' is written,

    When the group priority of a pending synchronous fault or supervisor call is lower than or equal to…

  • Cannot init heap using scatter file and C++ startup (Cortex-M4)

    Hello,

    I need help with heap initialization using scatter file and C++ startup.

    MCU is STM32F407VGT6 (Cortex-M4).

    Compiler is ARM Compiler 6.7, C++14.

    The problem is that all variables which I create dinamically on the heap have wrong addresses. My HEAP…

  • M4 Assembly - Set Enable also enables the Clear Enable Interrupt Register

    Hi,

    I have some assembly for Cortex M4 (Arm 7M Thumb), I want to enable an interrupt that is connected to a push button on an STM32 F407. It works, but for some reason when I enable the set enable register, the clear enable register also gets set ? Is…

  • Semihosting in DS-5

    Hi, I am trying to do file in DS-5 (evaluation version) using semihost, gettting errors (fopen returns -1). Is the eval version not able to do file IO?

  • what situation will the FPCA in Cortex-M4 change?

    Hi all,

    I'm study Cortex-M4 recently, and try to use floating point calculation,

    I read the book about that saying FPCA in control register will be set 1 after FPU work,

    but I'm not sure that when will FPCA be changed after set 1, or it will never…

  • Cortex-M7 VFMA usage

    Dear All,

    this is my first post and I hope I do not make any serious mistakes.

    My question is regarding the use case of the cortex-m7 VFMA/VMLA instruction.

    I am evaluating a polinomial for which the C compiler emits VFMA.F32 instructions. Out of curiosity…

  • cortex-m0 address branching from ROM to RAM

    I'm designing a MCU platform that is using ROM and RAM.

    My boot up scenario is as follows.

    First, ROM F/W is executed after power up(ROM F/W is excecuted only 1 time).

    And then, core waits for until program counter jump flag goes high at the end of ROM…

  • Cortex-M0 hangs up after soft reset

    We have a device which is used with NXP1115/303 MCU(cortex M0 core). Application doesn't do much, most of the time it sleeps in the deep power mode since the device  is on 3V lithium batery. The system do a soft reset every 30sec. Reset is implemen…

  • Assembler change immediate value of one assembly instruction

    I am using the KEIL MDK-5, assembly. The project compiles without some problems, but when i see the disassembly the assembler change the inmediate value

    Assembler substitute one instruction for another

    My code:

    The instruction: SUBS    R2,#0xC7

    the assembler…

  • Change Vector Table in cortex M4 in a persistent way

    Hello,

    I need to change the Vector Table but I need it to be persistent through a reset, what I'm trying to do is set a vector table duplicate as a safety measurement for reprogramming the original vector table.

    So far I being playing with the VTOR…

  • Does Documents have release Notes or update history?

    The G version has 410 pages!

    However, the H version reduce to 133 pages!

    It's like a big lost! 

    what's difference between the older and newer version?

    I think it's the ARM job to tell the difference. It's hard and wasting time for the user to…

  • Why Cortex-M7 doesn't support bit-banding?

    Cortex-M7 processors tends to be for the high performance applications. So why it doesn't support bit-banding if this has a lot of advantages to the code size and performance?

  • What happens to upper half of 32-bit data bus when reading 16-bit chip?

    Hi guys, I am interested in exploring a scenario when Cortex M4 cpu performs a 16-bit static memory read when 32-bit memory is actually on the board.

    The 16-bit memory chip is connected to lower half of the data bus, signals D0..D15 and there are two…

  • Is a DMB required between loading BASEPRI and storing BASEPRI_MAX?

    Hi,

    I have a question regarding BASEPRI, BASEPRI_MAX, and DMBs as they relate to both the V7-M and V7E-M architectures.

    Let's say I have the following assembly,

    // stuff
    mrs r0, BASEPRI
    msr BASEPRI_MAX, #3
    // more stuff

    Is it necessary to put a…

  • Using arm softcore in Kintex 7 board

    I am trying to use arm softcore along with my RTL in Kintex 7 board. What tool set is suggested? for both hardware and embedded development?

  • efficient c programming

    Hi everyone,

    I wonder if there is a documentation that explain how to program efficiently on arm cortex-m and arm cortex-r platform?

    I found "arm system developer's guide", but i worried it was too "old-fashion" because it only contained upto armv6..…

  • Bit-Banding. Only 1 bit at a time?

    Hi,
        I am developing a fixed-point MP3 & ACELP decoder on an Arduino Due. I realize that bit-banding makes a RMW sequence atomic but I notice fields in the Due hardware are multi-bit fields. Is there an atomic way to alter multiple bits? I realize that…

  • Interruptible Instructions on Cortex-M4

    The ARM Cortex-M4 Processor Technical Reference Manual states:

    To minimize interrupt latency, the processor abandons any divide instruction to take any pending interrupt. On return from the interrupt handler, the processor restarts the divide instruction…

  • Looking for typical max frequency for Cortex-M CPUs

    I'm looking for information on the typical max frequency (or typical frequency range) for the Cortex-M cores, in 40nm. Is there any documentation on that? Thanks.

  • Cortex-M23/M33 dynamic power

    I am doing a survey of the Cortex-M processors, and came across the M23/M33, which are described as having very low power like the M0. Are there some actual numbers (for example, with the smallest configuration, with TrustZone, in 28HPM or 40LP)? Or,…

  • Raising priority of PendSV within NVIC when PendSV pending

    Hi,

    I'm trying to understand the behavior of raising (lowering numerical priority) the priority of PendSV in the NVIC of a Cortex M4 or M7 when PendSV is already pending. Below are the cases I'm grappling with,

    1) High priority interrupt ISR is…

  • CortexM3

    I have a very simple CortexM3 based virtual platform example as below

    The amba_pv_m2 is connected to a memory in the top. The BusDecoder master port address range is 0x0-0x3FFFFFFF

    I have the following C program

    #include <stdio.h>

    int main(int…

  • CortexM3 : Issue when image start address is other than 0x0

    I have a very simple CortexM3 based virtual platform example as below

    The amba_pv_m2 is connected to a memory in the top. The BusDecoder master port address range is 0x0-0x3FFFFFFF

    I have the following C program

    #include <stdio.h>

    int main(int…