• Could anybody tell me how to boot up a processor in AARCH32 bit mode in Arm V8 and A53 core?

    can you please tell me how to boot up a processor in 32 bit mode for Armv8, A53 core using baremetal code?

    how can i know it is booted in 32bit mode?

    Thanks.

  • Cortex-A53 Cache protection

    Hello all,

    The "Core Technical Reference Manual" specifies in chapter 8.2 the error reporting mechanism for all types of uncorrectable errors in the caches, except for L1 D-cache data (which is SEC-DED) and for L1 D-cache dirty (which is SED-SEC) triggered…

  • MMU: force identity mapping without pages?

    hi,

    on a cortex a53, I would like to get the best of both worlds. Having dcache enabled but no page walk in case of a miss.

    I want no memory protection because we manage the whole system ( kind of baremetal processes)

    Is there a way to tell the mmu controller…

  • Arm a53: Populate TLB without table walk?

    Hi,

    From a previous question I got that setting the EPDx bits from the TCR_ELx register to 1 will disable table walk.

    Good starting point. But, should I access the same memory location again, it won't be in the TLB cache.

    How to work around that?

  • ARMv8-A CurrentEL Register Definition

    Where is the register definition of the CurrentEL register ?. I cannot seem to find it in the ARMv8A programming model guide or the Cortex-A53 TRM.

    . How does the PSTATE bits map to CurrentEL ?

    I read somewhere that a CurrentEL value of 0x4 denotes EL1…

  • What ARMv8.x revision Cortex-A35 is?

    Hi,

    ARMv8-A specification mentions revisions and options. I cannot find Cortex-A35 adheres to which exact version: ARMv8.1, 8.2, 8.3? I want to know which of the extensions described in the generic ARMv8-A spec are really available in that core.

    Thanks…

  • Multi core L1 cache coherent

    Dear experts,

     I'm going to implement multi-core(4 cortex-a53) in my private OS. I have an issue which needs your confirmation.

    Q. When core0 invalidates the L1-cache and L2-cache at VADDR(Cached), Can other cores  get the right data at VADDR ?

    For…

  • indirect branches in ARMv8

    Please clarify that with me... With

    "The current Program Counter (PC) cannot be referred to by number as if part of
    the general register file and therefore cannot be used as the source or destination
    of arithmetic instructions, or as the base, index…

  • Cortex-A7 Generic Timer Clock and Operation

    Hi,

         I'm using NXP imx6ul-evk(single core cortex-a7 processor) and I'm trying to operate CPU at different frequencies(642MHz, 480MHz, 100MHz, 12MHz) and experiencing time drift on certain frequencies (Generic Timer's time lags Real Time), I'm using virtual…

  • Trustzone FIQ latency measurement When security extension is enabled

    Hello Guys,

    Please refer below attached image. as shown in this image i want to measure the different latencies in my Trustzone based application.

    Here is the list of measurements which i want to perform.   

    1) FIQ latency when RTOS runs and FIQ occurs …

  • GIC-400 controller virtual interrupt handling in VM and hypervisor

    Hi, I am new to ARM architecture and as of now exploring GIC Controller GIC-400 and using ARM Cortex a57.

    Sorry for asking very fundamental flow of interrupts handling GIC-Virtual extension

    Let assume a physical interrupts acknowledged by hypervisor in…

  • which register are dedicated for each MPCore in ARMv8-A architecture?

    Hi  Expert,
    I'm a beginner to ARMv8-A architecture MPcore and now studying A35 MPCore processor documents for low-level software developing.
    One question, when I read DDI0487C_a_armv8_arm and DEN0024A_v8_architecture_PG, from my understanding, there…
  • How to access the system control register?

    Hi all,

    I am trying to access the system control register in my ARM C program. The code (with heading 64 bit) I used is presented below. However I got the following error message during compilation.

    /tmp/cc7Dc236.s: Assembler messages:
    /tmp/cc7Dc236.s:31…

  • Information about ARM System control registers.

    Hi all,

    I noticed there are multiple system control registers in ARM.

    The SCTLR_EL1 , SCTLR_EL2 and SCTLR_EL3.

    I want to know, what do multiple such system controls registers represent??

    I am particularly interested in the A bit of the system control register…

  • Feature Comparison ARM v8 series

    Hi Experts,

    Please specify is there any document on the Cortex A series comparison sheet for the various properties.

    For example, Table 2.1 in the https://static.docs.arm.com/den0024/a/DEN0024A_v8_architecture_PG.pdf has details on A53 and A57. Likewise…

  • ARMv7-A: Cache maintenance operation by VA, performance

    Hi,

    according to this talk, cache maintenance should always be performed by VA and not by set/way except during boot or shutdown. However, invalidating/cleaning a block of data by VA requires a loop to run over the entire memory block (in steps equal…

  • code is not working for optimization setting O2 and O3 for Arch64bit Cortex-A53 process

    I come across strange issue with Optimization setting O2 and O3 option my code will not work due to PC corruption, with O1 and O0 code woke fine, our target procesor is Arch64bit Cortex-A53. how to fix this issue. my i know what is the limitation of Heap…

  • Text section size for executable created with ARMCC 6.7 is more than expected

    Hi,

    I am porting Xilinx standalone drivers and libraries to armcc 6.7 compiler. I tried xilinx hello world application
    with the ported code base (for cortexa53 processor), and obseverd that text section size is ~82 KB. However, if i compile same hello…

  • AM3352 core hang-up

    Hello,

    We are encountering the core hang-up of unknown origin in our mass-produced board using TI's AM3352 and Linux Kernel 3.13.4.
    Regarding the reproducibility of the test, some units had the hang-up to take about 2000 hours after a system start…

  • Quad-Core Cortex A7 / MSDOS comparability

    I just bought a Samsung SM-T560 (WiFi) SM-T561 (3G & WiFi) with a 1.3GHz: Quad-Core Cortex A7. I know nothing about processors but in searching the Internet I have found some applications that will allow Windows OS to run an Android system.

    Is the 

  • To run library functions on arm a53 core

    Hello experts,
    I am working on a53 core in which I am not able to run string library functions like memset, memcpy etc. I have included the string.h library also but it is generation an exception. The same code works on the a15 core without any modification…

  • Ways to Tx data from Cortex R5 to A53?

    Hello,

    I'm trying understand the capabilities of both the cortex R5 and A53 but stuck at the point where i want to communicate to each core (A53 - Quad Cores and R5 - 2 Cores) in parallel. Can some one help me in understanding this or point to the related…

  • ARM MUL instruction

    Still more instruction things giving me head ache.

    This time it's the MUL-instruction.

    What the heck means:

    Multiply multiplies two register values. The least significant 32 bits of the result are written to the destination

    register. These 32 bits do…

  • ARM PMU access DRAM Event

    Hi, accorting to the reference manual of cortex A7 https://static.docs.arm.com/ddi0464/f/DDI0464.pdf

    pagina 243, what event number i neet to select to count all the DRAM access (read / write)?

  • Behavior for other data on a STR (ARMv7-A)

    When the following line is executed, what is the behavior with respect to the other words in the cache line?

    STR r1, [r0]

    The 4 bytes of data in r1 is written to the address in r0. But cache-lines are 32 bytes long. Assuming write-through (and ignoring…