• Intercore interrupts on a53 between EL1 and EL3

    We are working on Xilinx MPSOC which has 4 A53 cores, We are trying to run Linux(EL1) on 3 cores and Freertos(EL3) on 4th core. When software generated interrupts are raised from Linux , Freertos is not getting any interrupts. How to make interrupts work…

  • About watch point debug excption on Cortex-A53

    Now we are researching watch point function on A53. We simply write a driver, hook debug exception handler aml_watchpoint_handler instead of default watch point handler.

    In our watch point handler, we first disabled watch point control, then handle debug…

  • Cortex-A8 Pipelined cache maintenance

    Hi,

    I am new to the Cortex-A8,

    I would like to know what is the advantages of using "pipelined cache maintenance operations".

    "Auxiliary Control Register " has the  "Cache maintenance pipeline" bit enabled by default,
    is it recommended…

  • "CPSIE I"on an ARMv7A not changing the I bit in the CPSR register in USR mode - why?

    I'm using a CortexA8 and I can't seem to enable interrupts...! 

    I'm using a "CPSIE I" instruction, I can see that the compiler (GCC) is not optimizing my code out... I have to manually stop the program with a debugger and update the I bit myself…

  • Can Floating Point Unit(FPU) in cortexA9 processor raise an exception?

    Based on  ARM documents there is no exception ID for FPU (CortexA9) and just FPU instructions set exception flags in Floating-Point Status and Control Register (FPSCR). Is there a way to use these flags to raise an exception in the processor?

  • multi core programming

    hi 

     I have four functions and I am using cortex a7 processor. I want every core to execute one function. so to achieve this which registers and which manual and section should I refer too.

    i have placed one of my function say func1() at some address x…

  • Initial page table walk for secure/nonsecure accesses

    I have a basic concept question.  From what I read in the ARMv8 docs... there is an NS and NSTable bit in the page table entries themselves for the 2nd level and higher page table lookups.  So these can be used to block access ... I.e. NS access is attempting…

  • How to Write CP15 registers (CRn:C15) in Non-Secure mode

    Some of the Cortex-A8 registers like CP15 registers (CRn:C15) are writeable
    only in secure mode. How to write these registers when the CPU is in Non-Secure  mode?
    Please let me know if there is any reference example code on this.
    The Cortex-A8 manual mentions…

  • Precise abort vs synchronous abort in armv7

    I am new to arm architecture. I am reading exception handling from ARM cortex-A series programming guide. I have confusion about the technical difference between precise abort and synchronous abort or imprecise abort and synchronous abort. Are they refer…

  • SPI VIP

    how to implement the daisy chain concept in SPI vip?

  • SMP to suspend an individual core with security OS

    Hi All,

    a SMP architecture, like CA53-4core-mp, with a secure OS running at aa32 secure state.

    how to implement a suspend/resume flow on a individual core?

    TRM only mentions about how to clean cache and off-line from smp

    But how to do a cache flush through…

  • why inner attribute is affected by outer configuration?

    Hi expert:

    I am configuring a CortexA15 system. In the  LPAE page table entry, SH[1:0] is configured as 11, so this is a Inner Shareable field. Then I need to set MAIR0.attr0  which is used by stage 1 translation.  The problem is, my system behave differently…

  • Which is better of thees CPUs

    Which is better of thees CPUs:

    Cortex A53 octa core 1.5 ghz,

    Cortex A7 Allwinner T8 Eight core 2.0 ghz,

    Cortex A9 Quad-Core 1.8 ghz ?

  • Cortex-A15 MPCore: How to Enable Monitor Debug Mode

    Hi experts,

    I want to enable monitor debug mode for Cortex-A15 MPCore. I tried modifying DSCR[15] bit but watchpoint event still won't generate exception/abort. Core was in no-debug mode before modifying the DSCR (after power-on). I know I configured…

  • shareability attribute for armv8 cortex a-53

    Hi,

    I have a system with a multiple quad core clusters with Cortex A-53 and the CCN-512. L1 through L2 are integrated caches where L3 is an outer cache in 8xHN-F of the CCN512.

    My question is how should I interpret the shareability domain: inner, outer…

  • Cortex A7 - Boot from SPI NOR vs Execution In Place (XIP)

    Hi folks,

    I've been working for years with ARM -M processors and I'm facing -A processors for the first time.

    I fell in love with Allwinner's V3S processor which is v7-A type.

    The datasheet says that the processor is able to boot from an external…

  • Different performance in HYP and SVC mode ARMv7A?

    I'm doing some testing on Exynos5422 SoC which implements big.LITTLE architecture (A7 + A15), I'm running bare metal application which starts in HYP mode. I haven't returned from HYP mode by accident and then software delay which I implemented by simple…

  • Non-Cacheable memory and DMA on armv7a

    Hi !

    Consider a micro-kernel (not Linux) where device drivers are userland applications (PL0).

    We would like to use DMA based device, like an Ethernet controller for example. To this mean, the micro kernel allocate some memory to the user application…

  • ACP and DMA usage on A53

    Hi,

    I'm using DMA transfering data through ACP on A53. 

    According to A53 TRM, ACP burst size limits to 16B and 64B, does it mean the DMA connect to ACP also limited to transfer 64B data in max each time?

    Then software must re-configure DMA then re…

  • A53 preload mechanism

    Hi,

    I am reading the A53 MP Core doc.

    My question is related to instruction preloading in aarch64.

    In case of a very large block of code with no function calls, I want to make sure the L1 cache is always filled.

    Question 1:  Will the PLI instruction first…

  • MRS [A/C]PSR latency armv8-a?

    HI,

    Do anyone has a clue on the latency of the MRS CPSR (or APSR) command?

    I want to read the flags with no jump (and it is critical).

    Thanks

  • Data synchronization Barrier and cache.

    Hi, everybody. I have system based on multiprocessors system with ARMv7-A. I need copy table from one point of memory to another. I use for this task DMA. Memory attribute is write-back cacheable. Before starting copy by DMA, I clean data cache by MVA…

  • Cortex A15 vs A73 speed Odroid XU4(A15 1,8GHz) vs Hikey 960(A73 2,4GHz)

    I did some benchmark Odroid XU4(A15 1,8GHz) vs Hikey 960(A73 2,4GHz) 
    discuss.96boards.org/.../2140
    And I would expect better results
    but it looks like it is pretty much same if we have A15 on same frequency

    Anybody can explain this?

  • Is there any tool to profile power of a C code on Linux running on Cortex A53?

    We want to profile the power consumed by an application running over Linux kernel 4.2.x on Cortex A53. Is there any tool which can help here?

    regards,
    Ravi

  • Programming TZASC in Secure Mode

    Hi everyone,

    I am working to setup the TZASC on I.MX6UL based dev platform platform.

    I did the following.

    - Running SPL bootloader from OCRAM

    - Disable the bypass (by setting GPR9's bit 0 to 1 on my boards).

    - Setup 2 regions

           * Region 0 - Base…