As I know, Cortex-R5MP supports lock-step mode and every output from two cores will be compared in this mode.
I'm curious about the handling of Interrupt Service Routine during the lock-step mode.
When these two cores share same interrupt input, how can they execute same interrupt service routine without occuring lock-step fault?
It is not a few cycles, only a half cycle. It is like a black box. There is one(!) interrupt line, which enters the box. The two cores (actually no master/no checker) get this input and work with it. The delay is needed to find transient issues, so in the end I think it is no difference if half cycle or multiple.Important is, that both cores have the very same input.
Thank you so much for your reply. :)