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Is that possible for Cortex-R5's dual-core to handle interrupt during lock-step mode?

As I know, Cortex-R5MP supports lock-step mode and every output from two cores will be compared in this mode.

I'm curious about the handling of Interrupt Service Routine during the lock-step mode.

When these two cores share same interrupt input, how can they execute same interrupt service routine without occuring lock-step fault?

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  • Let me explain why I thought lock-step fault would be occurred when some interrupt input occurred into two cores during the lock-step mode.

    I heard that these two cores, Master Core and Checker Core, perform same instructions and Checker Core follows Master Core's operation with few cycles time offset.

    If some interrupt input is coccurred during this time offset between Master Core and Checker Core, Checker Core's PC would be jumped to Interrupt Service Routine before finishing the comparison of two core's operation. 

    This is why I thought that. :)

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  • Let me explain why I thought lock-step fault would be occurred when some interrupt input occurred into two cores during the lock-step mode.

    I heard that these two cores, Master Core and Checker Core, perform same instructions and Checker Core follows Master Core's operation with few cycles time offset.

    If some interrupt input is coccurred during this time offset between Master Core and Checker Core, Checker Core's PC would be jumped to Interrupt Service Routine before finishing the comparison of two core's operation. 

    This is why I thought that. :)

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