As I know, Cortex-R5MP supports lock-step mode and every output from two cores will be compared in this mode.
I'm curious about the handling of Interrupt Service Routine during the lock-step mode.
When these two cores share same interrupt input, how can they execute same interrupt service routine without occuring lock-step fault?
In Lock-Step mode both cores act as one core. No software can distinct between the two cores. IIRC there is only one bus to the "outside" of the core, so both cores get the same inputs.