Is that possible for Cortex-R5's dual-core to handle interrupt during lock-step mode?

As I know, Cortex-R5MP supports lock-step mode and every output from two cores will be compared in this mode.

I'm curious about the handling of Interrupt Service Routine during the lock-step mode.

When these two cores share same interrupt input, how can they execute same interrupt service routine without occuring lock-step fault?