I am currently working on the cortex R5 and I am wondering its behavior when a masked imprecise abort occurs. Indeed, The A-bit in the CPSR is set by default. Which mean that imprecise abort will be masked.
My problem is to understand in which state will be the core after a masked asynchronous abort. Can we imagine it will infinitely loop on the instruction responsible for the abort ? Maybe it will just ignore the instruction ?
I did not find answers among documentations so I ask for your help.
Quick word on terminology. All imprecise exceptions are asynchronous, not all asynchronous exceptions are imprecise. It is asynchronous exceptions which the CPSR flags mask.
If the processor receives an asynchronous exception while that exception type is masked, then the processor will simply continue executing as normal. This is true for interrupts (IRQ and FIQ) and also async aborts.
By their nature, there is no way of the processor knowing whether an async abort has anything to do with the instruction being executed currently. It's quite possible (likely?) that the current instruction is unrelated.
In order to complete my understanding on this type of error, let's me give you an example.
According to documentation, in the specific case where the asynchronous abort is due to an error on cache line eviction, the evicted cache line is not written in memory.
Regarding your answer, that means that the new line will overwrite the corrupted evicted cache line and thus data definitively lost. Could you confirm this specific behavior ?
A 2-bit ECC error on a dirty cache line does mean that you have potentially lost (or corrupted) data. The abort is the way the processor tells you that this has happened. If you choose ignore/mask the abort, then - yes - this could lead to the line with the error being re-loaded from memory. But really you lost the data due the 2-bit error, not the cache line re-load.
Note, the R5 has the option of forcing write-through behaviour on the caches. This means you could avoid this scenario.
We have a related question: can asynchronous aborts be pending? Our experiments on a Cortex-R5 shows that yes: if the code generating the async abort is executed while CPSR.A=1, then the abort is taken once the A bit is unmasked. However, this is strange because there is no pending status flag for that interrupt...
Also, before unmasking CPSR.A, is it possible to look to a register to know if we'll get an exception upon unmasking it? That is possible with CPSR.I/F by looking at status registers in the IRQ/FIQ interrrupt controller. If not, that may be a problem for an RTOS: it wants to make sure no errors are pending before unmasking interrupts to launch a task.
When an asynchronous abort occurs, is it memorized in the Cortex-R5 core in some hidden bit / latch? It seems so because external peripherals do not keep that information.
Related to that, I couldn't find in Cortex-R5 TRM r1p2 Annex A "Signal Descriptions" a signal for external asynchronous aborts. Is it through BRESPMm/RRESPMm AXI signals?
Wow, old thread.
Yes, an async abort will be pended until it can be taken (i.e. the CPSR.A bit cleared). In terms of checking for async aborts, later processors have the ISR register, which lets you do this. But I don't believe it is present on the Cortex-R5.
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