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Cortex R5 behavior when a masked imprecise/asynchronous abort occurs

Hello,

I am currently working on the cortex R5 and I am wondering its behavior when a masked imprecise abort occurs. Indeed, The A-bit in the CPSR is set by default. Which mean that imprecise abort will be masked.

My problem is to understand in which state will be the core after a masked asynchronous abort. Can we imagine it will infinitely loop on the instruction responsible for the abort ? Maybe it will just ignore the instruction ?

I did not find answers among documentations so I ask for your help.

Thanks you.

Antoine

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  • Quick word on terminology.  All imprecise exceptions are asynchronous, not all asynchronous exceptions are imprecise.  It is asynchronous exceptions which the CPSR flags mask.

    If the processor receives an asynchronous exception while that exception type is masked, then the processor will simply continue executing as normal.  This is true for interrupts (IRQ and  FIQ) and also async aborts.

    By their nature, there is no way of the processor knowing whether an async abort has anything to do with the instruction being executed currently.  It's quite possible (likely?) that the current instruction is unrelated.

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  • Quick word on terminology.  All imprecise exceptions are asynchronous, not all asynchronous exceptions are imprecise.  It is asynchronous exceptions which the CPSR flags mask.

    If the processor receives an asynchronous exception while that exception type is masked, then the processor will simply continue executing as normal.  This is true for interrupts (IRQ and  FIQ) and also async aborts.

    By their nature, there is no way of the processor knowing whether an async abort has anything to do with the instruction being executed currently.  It's quite possible (likely?) that the current instruction is unrelated.

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